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    SMALLEST OR LARGEST VALUE ELEMENT DETERMINATION
    1.
    发明申请
    SMALLEST OR LARGEST VALUE ELEMENT DETERMINATION 有权

    公开(公告)号：US20210294606A1

    公开(公告)日：2021-09-23

    申请号：US17339691

    申请日：2021-06-04

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F9/30 ,  G06F15/78

    Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

    Apparatuses and methods for performing corner turn operations using sensing circuitry
    3.
    发明授权
    Apparatuses and methods for performing corner turn operations using sensing circuitry 有权

    公开(公告)号：US10699756B2

    公开(公告)日：2020-06-30

    申请号：US16215122

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C8/16 ,  G11C8/10 ,  G11C15/04

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

    Multiplication operations in memory
    5.
    发明授权
    Multiplication operations in memory 有权

    公开(公告)号：US10409555B2

    公开(公告)日：2019-09-10

    申请号：US15905083

    申请日：2018-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F7/523 ,  G06G7/16 ,  G06F7/53 ,  H03K19/177 ,  G11C7/10 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

    ELEMENT VALUE COMPARISON IN MEMORY
    6.
    发明申请
    ELEMENT VALUE COMPARISON IN MEMORY 审中-公开

    公开(公告)号：US20190103141A1

    公开(公告)日：2019-04-04

    申请号：US16207284

    申请日：2018-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/06 ,  G11C11/4096 ,  G11C11/4091 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

    Loop structure for operations in memory
    9.
    发明授权
    Loop structure for operations in memory 有权

    公开(公告)号：US10176851B2

    公开(公告)日：2019-01-08

    申请号：US15442086

    申请日：2017-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

    IPC: G11C7/10 ,  G11C8/04 ,  G11C7/00 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

    Element value comparison in memory
    10.
    发明授权
    Element value comparison in memory 有权

    公开(公告)号：US10147467B2

    公开(公告)日：2018-12-04

    申请号：US15489342

    申请日：2017-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/06 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

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