公开(公告)号：US11797385B2

公开(公告)日：2023-10-24

申请号：US17510135

申请日：2021-10-25

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/108 ,  G06F11/076 ,  G06F11/0772

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

公开(公告)号：US20230060913A1

公开(公告)日：2023-03-02

申请号：US17459808

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Francesco Lupo

IPC: G06F3/06

Abstract: A method includes determining respective health characteristic values of blocks of non-volatile memory cells, determining, based on the respective health characteristic values and at least one effective health factor of the blocks of the non-volatile memory cells, effective respective health characteristic values of the blocks of non-volatile memory cells, and based on the effective respective health characteristic values, performing a media management operation involving a block of non-volatile memory cells of the blocks of non-volatile memory cells having an effective respective health characteristic value that is greater than a health criterion.

公开(公告)号：US12019877B2

公开(公告)日：2024-06-25

申请号：US17813286

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for metadata allocation in memory systems are described. Different blocks of a memory device of the memory system may be utilized for storing different types of data. For example, a first block may be utilized to store journaling data and a second block to store data (e.g., user data) received from a host system. The first block may include memory cells operable as high endurance single-level cells, and may be configured to support a high frequency of write operations of data with low retention rates. Additionally, the second set of block may include memory cells (e.g., a high density of memory cells) operable as multiple-level cells, and may be configured to retain large quantities of data.

公开(公告)号：US20230317135A1

公开(公告)日：2023-10-05

申请号：US17713641

申请日：2022-04-05

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Christopher Joseph Bueb

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/40622

Abstract: Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.

公开(公告)号：US20230317134A1

公开(公告)日：2023-10-05

申请号：US17712972

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4074

Abstract: Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.

公开(公告)号：US20230132223A1

公开(公告)日：2023-04-27

申请号：US17510135

申请日：2021-10-25

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

公开(公告)号：US11599273B2

公开(公告)日：2023-03-07

申请号：US16625130

申请日：2019-01-29

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Alberto Troia

IPC: G06F3/06

Abstract: An example method for managing a memory device includes a non-volatile memory. The example method further includes providing a first time-stamp to the memory device, wherein the first time-stamp is a power-down time-stamp of the memory device, storing the first time-stamp, associating the first time-stamp with at least one region of the non-volatile memory, providing a second time-stamp to the memory device, wherein the second time-stamp is a subsequent power-up time-stamp of the memory device, associating the second time-stamp with the at least one region of the non-volatile memory, determining a difference time between the first time-stamp and the second time-stamp, and, based on the difference time, performing a refresh operation of the at least one region of the non-volatile memory. Further, a related memory device is disclosed, as well as a method for measuring the off-time of a memory device.

公开(公告)号：US20220342819A1

公开(公告)日：2022-10-27

申请号：US17241850

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Binbin Huo

IPC: G06F12/0804 ,  G01K3/06

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.