公开(公告)号：US20060034410A1

公开(公告)日：2006-02-16

申请号：US10533507

申请日：2003-10-08

Applicant: Mihai Sanduleanu ,  Dominicus Leenaerts

Inventor： Mihai Sanduleanu ,  Dominicus Leenaerts

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L2207/06 ,  H04L7/0274

Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).

Abstract translation: 一种锁相环（1），包括包括平衡四极管相关器（2）的频率检测器（10），所述环路（1）的特征在于所述四极管相关器（2）包括双边沿时钟双稳态电路（21,22,23 ，24,25,26,27,28）由耦合到多路复用器（31,32,33,34）的信号由与输入D信号（D）具有相同比特率的信号控制。

公开(公告)号：US20070285119A1

公开(公告)日：2007-12-13

申请号：US11572915

申请日：2005-07-18

Applicant: Mihai Sanduleanu ,  Eduard Stikvoort

Inventor： Mihai Sanduleanu ,  Eduard Stikvoort

IPC: H03K19/01

CPC classification number: H03K19/0948 ,  H03K19/082 ,  H03K19/1738 ,  H03K19/215

Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q−) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q−) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).

Abstract translation: 公开了一种组合逻辑电路，其包括经由第一电阻器（RI）耦合到电源端子（V SUB）的第一逻辑块（B 1）和经由第二电阻器装置（R 2） 用于接收相应的第一和第二电源电流（111,112）。 电路还包括经由第一电阻器装置（R 1）和经由第二电阻器装置（R 2）耦合到电源端子（V SUB）的第二逻辑块（B 2），用于接收相应的 第三和第四电源电流（122,121）。 耦合到第一块（B1）和第一电阻器装置（R 1）的第一输出端（Q-）。 耦合到第二逻辑块（B 2）和第二电阻器装置（R 2）的第二输出端子（Q +）。 耦合到第一输出端（Q-）和/或第二输出端（Q +）中的至少一个的第一电流源（I 0），用于通过第一电阻器装置（R1）提供第一电源电流（I 1） ，其基本上等于通过第二电阻器装置（R 2）的第二电源电流（I 2）。

公开(公告)号：US20070021933A1

公开(公告)日：2007-01-25

申请号：US10569125

申请日：2004-08-11

Applicant: Mihai Sanduleanu ,  Eduard Stikvoort

Inventor： Mihai Sanduleanu ,  Eduard Stikvoort

IPC: G01R29/26 ,  G01R29/02

CPC classification number: H03D13/003 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/107 ,  H04L7/033

Abstract: The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A transition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector comprises a first signal generator (42) for generating a first binary signal ERRQ, a pulse width of which is equal to a first time difference ΔT1 between a transition of the data signal DATA and a transition of a first reference clock signal CKQ adjacent to the transition of the data signal DATA, wherein the first signal generator comprises an input for receiving the first reference clock signal CKQ and an input for receiving the data signal DATA. The phase detector comprises a second signal generator (40) for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ΔT2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA, wherein the second signal generator (40) comprises an input for receiving the second binary signal ERRI and an input for receiving the second reference signal CKI. The phase detector comprises an output signal generator (40) for generating an output signal representative of the phase difference between the data clock DATA-CLK and the reference clock REF-CLK, wherein the output signal is equal to ERRQ−2*(ERRQ AND ERRI) and AND represents a logical AND-operation or the output is equal to (ERRQ XOR ERRI)−ERRI, wherein XOR represents a logical XOR-operation.

Abstract translation: 本发明涉及一种用于使用数据信号DATA检测数据时钟DATA-CLK和参考时钟REF-CLK之间的相位差的相位检测器。 数据信号DATA的转换与数据时钟DATA-CLK的转换同步。 数据时钟DATA-CLK和参考时钟REF-CLK具有相同的频率。 相位检测器包括用于产生第一二进制信号ERRQ的第一信号发生器（42），其中脉冲宽度等于数据信号DATA的转变和第一参考时钟信号的转变之间的第一时间差ΔT1 CKQ与数据信号DATA的转换相邻，其中第一信号发生器包括用于接收第一参考时钟信号CKQ的输入端和用于接收数据信号DATA的输入端。 相位检测器包括用于产生第二二进制信号ERRI的第二信号发生器（40）。 第二二进制信号ERRI的脉冲宽度等于数据信号DATA的转变与与数据信号DATA的转变相邻的第二参考时钟信号CKI的转变之间的第二时间差ΔT2，其中第二信号 发生器（40）包括用于接收第二二进制信号ERRI的输入端和用于接收第二参考信号CKI的输入端。 相位检测器包括用于产生表示数据时钟DATA-CLK与参考时钟REF-CLK之间的相位差的输出信号的输出信号发生器（40），其中输出信号等于ERRQ-2 *（ERRQ AND ERRI），AND表示逻辑AND运算，或者输出等于（ERRQ XOR ERRI）-ERRI，其中XOR表示逻辑异或运算。

公开(公告)号：US20060208769A1

公开(公告)日：2006-09-21

申请号：US10550345

申请日：2004-03-22

Applicant: Mihai Sanduleanu ,  Eduard Stikvoort

Inventor： Mihai Sanduleanu ,  Eduard Stikvoort

IPC: G11C27/02

CPC classification number: G11C27/024 ,  G01R25/005 ,  H03L7/085 ,  H03L7/087 ,  H04L7/033

Abstract: A tracking data cell (10) comprising: —a pair of track and hold circuits (1, 1′) coupled to a first multiplexer (5), —a clock signal (H+, H−) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1′) for determining a receipt of a data signal (D+, D−) having a rate, —said track and hold circuits (1, 1′) providing an output signal (O) having a substantially half rate.

Abstract translation: 一种跟踪数据单元（10），包括： - 耦合到第一多路复用器（5）的一对跟踪和保持电路（1,1'）， - 时钟信号（H +，H-）基本上被反相输入 用于确定具有速率的数据信号（D +，D-）的接收的相应的跟踪和保持电路（1,1'），提供输出信号（1），提供输出信号（1） 大概是一半的。

公开(公告)号：US20060006954A1

公开(公告)日：2006-01-12

申请号：US10527946

申请日：2003-08-06

Applicant: Mihai Sanduleanu

Inventor： Mihai Sanduleanu

IPC: H03B5/00

CPC classification number: H03L7/107 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/1243 ,  H03L7/0893 ,  H03L7/095 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/06

Abstract: Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means (2) and characterized in that the modulator means (2) are coupled to amplifier means (1) via an adder (3) for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (VT) provided to the modulator means (2).

Abstract translation: 压控振荡器包括耦合到调制器装置（2）的LC谐振电路（L，C，R），其特征在于调制器装置（2）经由加法器（3）耦合到放大器装置（1），用于产生正交 周期性输出信号具有相对宽的范围内的频率，该频率由提供给调制器装置（2）的控制信号（V SUB）控制。