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40 条记录 (耗时 0.025 秒)

    Method for synchronizing sampling to sinusoidal inputs
    1.
    发明授权
    Method for synchronizing sampling to sinusoidal inputs 有权
    用于将采样同步到正弦输入的方法

    公开(公告)号：US08587351B1

    公开(公告)日：2013-11-19

    申请号：US13469446

    申请日：2012-05-11

    申请人： Adam Crandall

    发明人： Adam Crandall

    IPC分类号： H03L7/06

    CPC分类号： H04L7/0274 ,  H03L7/0812 ,  H03M1/1255 ,  H04L2007/047

    摘要： A method for synchronizing input sampling to desired phase angles of sinusoidal signals including determining a delay time period for converging a next sample point to a next desired phase angle based on a phase error value.

    摘要翻译： 一种用于将输入采样与期望的正弦信号相位角同步的方法，包括基于相位误差值确定用于将下一采样点收敛到下一个所需相位角的延迟时间段。

    Methods and systems for adaptive receiver equalization
    2.
    发明授权
    Methods and systems for adaptive receiver equalization 有权
    自适应接收机均衡的方法和系统

    公开(公告)号：US08223828B2

    公开(公告)日：2012-07-17

    申请号：US11976185

    申请日：2007-10-22

    申请人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

    发明人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

    摘要翻译： 用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。 在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。 自适应控制逻辑由模拟和/或数字组件实现。 在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。 在一个实施例中，本发明数字地控制均衡参数。 在一个实施例中，所得到的均衡的模拟数据信号被数字化。 在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。 然后将均衡的样品数字化。 本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

    Carrier reproduction circuit, receiver, loop filter circuit, and oscillator circuit
    3.
    发明授权
    Carrier reproduction circuit, receiver, loop filter circuit, and oscillator circuit 失效
    载波再生电路，接收机，环路滤波电路和振荡电路

    公开(公告)号：US06810097B1

    公开(公告)日：2004-10-26

    申请号：US09705688

    申请日：2000-11-03

    申请人： Taku Yamagata

    发明人： Taku Yamagata

    IPC分类号： H03D324

    CPC分类号： H04L1/0057 ,  H03L7/0991 ,  H03M13/2707 ,  H03M13/2936 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/0071 ,  H04L1/0072 ,  H04L1/0075 ,  H04L7/0274 ,  H04L27/0012 ,  H04L27/2273 ,  H04L2001/0093 ,  H04L2027/0069 ,  H04N19/89 ,  H04N21/2383 ,  H04N21/4382

    摘要： A carrier reproduction circuit comprising a complex multiplier circuit for generating a first signal by detecting a difference between a received signal and a signal fed back at a Costas loop circuit, a loop filter circuit for generating a second signal by processing the first signal by using a first integration loop containing a first delay circuit for giving one-symbol's worth of a delay, and an NCO circuit for feeding back the signal generated by processing the second signal by using a second integration loop containing a second delay circuit for giving one-symbol's worth of delay toward the complex multiplier circuit and switching the loop filter circuit and the NCO circuit to a state 12 symbols before in accordance with a TMCC detection signal and thereby capable of performing the carrier reproduction of the received signal at a high speed and with a high precision.

    摘要翻译： 一种载波再现电路，包括：复数乘法电路，用于通过检测接收信号和在科斯塔斯环路电路反馈的信号之间的差来产生第一信号;环路滤波器电路，用于通过使用第一信号来处理第一信号来产生第二信号 包含用于给出一个符号的延迟的第一延迟电路的第一积分回路和用于通过使用包含第二延迟电路的第二积分回路来反馈由第二信号处理产生的信号的NCO电路，用于给予一个符号的价值 对复合乘法器电路的延迟，并根据TMCC检测信号将环路滤波器电路和NCO电路切换到12个符号状态，从而能够以高速和高电平执行接收信号的载波再现 精确。

    Clock synchronizing circuit
    4.
    发明授权
    Clock synchronizing circuit 失效
    时钟同步电路

    公开(公告)号：US06539070B1

    公开(公告)日：2003-03-25

    申请号：US09440522

    申请日：1999-11-15

    申请人： Yoshikazu Kakura ,  Tomoki Osawa

    发明人： Yoshikazu Kakura ,  Tomoki Osawa

    IPC分类号： H04C700

    CPC分类号： H04L7/0274

    摘要： A clock synchronizing circuit enables initial synchronization of clock in spite of the case of modulation system except for quadrature modulation with simple constitution. A cosine/sine output circuit inputs thereto an integration clock ‘ICLK’, a sampling signal ‘SSAMP’, a sign switching signal ‘SPM’, a cosine component integration signal ‘SCCI’, and a sine component integration signal, before obtaining a cosine signal ‘SCOS’ corresponding to a cosine component of initial phase of a symbol clock and a sine signal ‘SSIN’ corresponding to a sine component thereof. An angular detector inputs thereto the cosine signal ‘SCOS’ and the sine signal ‘SSIN’, before obtaining initial phase of the symbol clock ‘SCLK’.

    摘要翻译： 尽管调制系统的情况除了采用简单结构的正交调制之外，时钟同步电路能够实现时钟的初始同步。 余弦/正弦输出电路在获得余弦值之前向其输入积分时钟“ICLK”，采样信号“SSAMP”，符号切换信号“SPM”，余弦分量积分信号“SCCI”和正弦分量积分信号 对应于符号时钟的初始相位的余弦分量的信号“SCOS”和对应于其正弦分量的正弦信号“SSIN”。 在获得符号时钟“SCLK”的初始相位之前，角度检测器向其输入余弦信号“SCOS”和正弦信号“SSIN”。

    PLL using unbalanced quadricorrelator
    7.
    发明授权
    PLL using unbalanced quadricorrelator 失效
    PLL使用不平衡二次相关器

    公开(公告)号：US07804926B2

    公开(公告)日：2010-09-28

    申请号：US10533058

    申请日：2003-10-08

    申请人： Mihai Adrian Tiberiu Sanduleanu

    发明人： Mihai Adrian Tiberiu Sanduleanu

    IPC分类号： H03D3/24

    CPC分类号： H03L7/087 ,  H03D13/003 ,  H03L7/091 ,  H03L2207/06 ,  H04L7/0274

    摘要： A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).

    摘要翻译： 一种用于数据和时钟恢复的锁相环（1），包括包括二次相关器（2）的频率检测器（10），所述四相关器（2）包括频率检测器，所述频率检测器包括双边沿时钟双稳态电路（21,22， 耦合到第一多路复用器（31）的第二多路复用器（32）和由具有与输入信号（D）相同的比特率的信号控制的第二多路复用器（32），以及由第一信号对（D）控制的相位检测器 （PQ，PQ由第一多路复用器31提供）和由第二多路复用器（32）提供的第二信号对（PI，PI）。

    Timing recovery and phase tracking system and method
    10.
    发明申请
    Timing recovery and phase tracking system and method 失效
    定时恢复和相位跟踪系统及方法

    公开(公告)号：US20020044617A1

    公开(公告)日：2002-04-18

    申请号：US09844296

    申请日：2001-04-30

    发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Josephus Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

    IPC分类号： H04L007/00

    CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

    摘要翻译： 高速串行数据收发器包括多个接收器和发送器，用于以千兆比特每秒的数据速率接收和发送多个模拟串行数据信号。 每个接收机包括用于跟踪与接收机相关联的串行数据信号的相位和频率的定时恢复系统。 定时恢复系统包括响应于相位控制信号的相位内插器和具有不同预定相位的一组参考信号。 相位内插器导出具有内插相位的采样信号以采样串行数据信号。 每个接收机中的定时恢复系统独立地对采样信号和与接收机相关联的串行数据信号进行频率同步。 接收机可以包括多个路径，用于根据多个具有内插相位的多个时间交错采样信号对接收的串行数据信号进行采样。