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20 条记录 (耗时 0.021 秒)

    Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec
    11.
    发明授权
    Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec 有权
    用于计算机系统的唤醒电路，使得编解码器控制器能够响应于由编解码器检测到唤醒事件而产生系统中断

    公开(公告)号：US06564330B1

    公开(公告)日：2003-05-13

    申请号：US09472096

    申请日：1999-12-23

    申请人： Alberto J. Martinez ,  David I. Poisner ,  Karthi R. Vadivelu

    发明人： Alberto J. Martinez ,  David I. Poisner ,  Karthi R. Vadivelu

    IPC分类号： G06F126

    CPC分类号： G06F1/24

    摘要： A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.

    摘要翻译： 用于具有编解码器控制器的计算机系统的唤醒电路。 当编解码器检测到需要系统激活的事件时，该电路向计算机系统提供唤醒信号。 提供该信号是否编解码器与其控制器之间的通信链路是活动的还是非活动的。 当链路处于非活动状态时，如没有位时钟所示，任何编解码器输入线上的数据信号触发控制器向系统发送电源激活信号并启动编解码器链路的激活。 如果链路已经处于活动状态，则通用输入状态改变位被发送到控制器，控制器将其写入用于触发系统功率激活信号的寄存器。 启用输入允许在程序控制下启用或禁用唤醒信号。 唤醒信号可用于触发适用于启动系统恢复功能的系统管理中断或其他中断。

    Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates
    13.
    发明授权
    Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates 有权
    针对具有不均匀帧速率的多个USB控制器进行功率优化的帧同步

    公开(公告)号：US08347015B2

    公开(公告)日：2013-01-01

    申请号：US13305591

    申请日：2011-11-28

    申请人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    发明人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    IPC分类号： G06F13/14 ,  G06F3/00

    CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

    摘要翻译： 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

    Configurable controller for audio channels
    14.
    发明授权
    Configurable controller for audio channels 失效
    用于音频通道的可配置控制器

    公开(公告)号：US06629001B1

    公开(公告)日：2003-09-30

    申请号：US09396979

    申请日：1999-09-15

    申请人： Karthi R. Vadivelu

    发明人： Karthi R. Vadivelu

    IPC分类号： G06F1700

    CPC分类号： G06F3/16

    摘要： The present invention is a method and apparatus to control audio channels. Configuration registers configure usage of the audio channels. A plurality of channel logic circuits are coupled to the corresponding configuration registers to provide logic functions to the audio channels according to the configured usage.

    摘要翻译： 本发明是一种控制音频通道的方法和装置。 配置寄存器配置音频通道的使用。 多个通道逻辑电路耦合到相应的配置寄存器，以根据配置的使用向音频通道提供逻辑功能。

    POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS WITH NON-UNIFORM FRAME RATES
    17.
    发明申请
    POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS WITH NON-UNIFORM FRAME RATES 有权
    具有非均匀帧速率的多个USB控制器的功率优化帧同步

    公开(公告)号：US20120072636A1

    公开(公告)日：2012-03-22

    申请号：US13305591

    申请日：2011-11-28

    申请人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    发明人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    IPC分类号： G06F13/28

    CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

    摘要翻译： 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

    Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates
    18.
    发明授权
    Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates 有权
    针对具有不均匀帧速率的多个USB控制器进行功率优化的帧同步

    公开(公告)号：US08069294B2

    公开(公告)日：2011-11-29

    申请号：US11395678

    申请日：2006-03-30

    申请人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    发明人： Michael N. Derr ,  Darren L. Abramson ,  Bryan C. Doucette ,  Karthi R. Vadivelu

    IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/00 ,  H04L1/00

    CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

    摘要翻译： 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

    Method and apparatus for obtaining coherent accesses with posted writes from multiple software drivers
    19.
    发明授权
    Method and apparatus for obtaining coherent accesses with posted writes from multiple software drivers 有权
    用于通过来自多个软件驱动程序的贴写获得一致访问的方法和装置

    公开(公告)号：US06453375B1

    公开(公告)日：2002-09-17

    申请号：US09275361

    申请日：1999-03-23

    申请人： Michael N. Derr ,  Karthi R. Vadivelu

    发明人： Michael N. Derr ,  Karthi R. Vadivelu

    IPC分类号： G06F1200

    CPC分类号： G06F13/102

    摘要： A method and apparatus that may be used to obtain coherent accesses with posted writes. One method disclosed involves returning a semaphore indicator in an unlocked state and setting the semaphore indicator to a locked state in response to a semaphore indicator read when the semaphore indicator is in an unlocked state. A cycle for a target from a source is stored in an interface circuit, and the semaphore indicator is cleared to the unlocked state after the cycle completes to the target.

    摘要翻译： 可用于通过发布的写入获得一致访问的方法和装置。 所公开的一种方法包括将信号量指示符返回到解锁状态，并且当信号量指示器处于未锁定状态时响应于信号量指示符读取将信号量指示符设置为锁定状态。 来自源的目标的周期存储在接口电路中，并且信号量指示符在循环完成到目标之后被清除为解锁状态。