公开(公告)号：US20120134220A1

公开(公告)日：2012-05-31

申请号：US13111231

申请日：2011-05-19

申请人： Young Seog KIM ,  Young Suk KIM

发明人： Young Seog KIM ,  Young Suk KIM

IPC分类号： G11C7/12 ,  G11C8/08

CPC分类号： G11C11/419 ,  G11C8/08

摘要： A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger.

摘要翻译： 电路包括用于驱动世界线的字线驱动器和用于驱动跟踪字线的跟踪字线驱动器。 世界线上的世界线信号的脉冲宽度被驱动为大于跟踪世界线上的跟踪世界线信号的脉冲宽度，以帮助在困难条件下进行写入。 由于跟踪字线信号比字线信号被激活的时间晚，而且与字线同时被去激活，所以字线信号的脉冲宽度较大。

公开(公告)号：US20120019312A1

公开(公告)日：2012-01-26

申请号：US12843366

申请日：2010-07-26

申请人： Young Seog KIM ,  Kuoyuan (Peter) HSU ,  Derek C. TAO ,  Young Suk KIM

发明人： Young Seog KIM ,  Kuoyuan (Peter) HSU ,  Derek C. TAO ,  Young Suk KIM

IPC分类号： G05F3/02

CPC分类号： G11C11/412

摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

公开(公告)号：US20120014201A1

公开(公告)日：2012-01-19

申请号：US12835197

申请日：2010-07-13

申请人： Derek C. TAO ,  Kuoyuan (Peter) HSU ,  Dong Sik JEONG ,  Young Suk KIM ,  Young Seog KIM ,  Yukit TANG

发明人： Derek C. TAO ,  Kuoyuan (Peter) HSU ,  Dong Sik JEONG ,  Young Suk KIM ,  Young Seog KIM ,  Yukit TANG

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.

摘要翻译： 一种存储器，包括：布置成多行和多列的多个存储单元。 所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或 该列中的多个存储单元的第二电压和多个内部接地节点。 内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

公开(公告)号：US20100297821A1

公开(公告)日：2010-11-25

申请号：US12852805

申请日：2010-08-09

申请人： Young Suk KIM

发明人： Young Suk KIM

IPC分类号： H01L21/335 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate; and forming a semiconductor lager in the element region at both sides of the gate electrode apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.

摘要翻译： 一种制造应用技术的半导体器件的制造方法，其中可以抑制由硅化引起的漏电流。 该方法包括在半导体衬底中形成隔离区; 在由形成在半导体衬底中的隔离区限定的元件区域上形成栅电极; 以及在所述隔离区域的至少一部分的所述栅电极的两侧的所述元件区域中形成半导体层。 通过这样做，即使形成硅化物层，也抑制了隔离区附近的尖峰的形成。 因此，可以抑制由这种尖峰引起的漏电流。

公开(公告)号：US20090095982A1

公开(公告)日：2009-04-16

申请号：US12205074

申请日：2008-09-05

申请人： Young Suk KIM

发明人： Young Suk KIM

IPC分类号： H01L29/737 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.

摘要翻译： 应用技术的半导体器件可以抑制由硅化产生的漏电流。 栅极电极形成在由形成在半导体衬底中的隔离区限定的元件区域上，栅绝缘膜在其间。 延伸区域和源极/漏极区域形成在栅电极两侧的元件区域中。 此外，与晶格常数的半导体衬底不同的半导体层与隔离区域的至少一部分分开形成。 通过这样做，即使形成硅化物层，也抑制了隔离区附近的尖峰的形成。 因此，可以抑制由这种尖峰引起的漏电流。