公开(公告)号：US06008684A

公开(公告)日：1999-12-28

申请号：US735894

申请日：1996-10-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H03K17/567 ,  H03K19/003 ,  H03K19/017 ,  H03K19/098 ,  H03K17/687

CPC分类号： H03K19/098 ,  H03K17/567 ,  H03K19/00315 ,  H03K19/01721

摘要： An MOS-controlled, lateral SCR device including a semiconductor substrate of a first doping type; a first well region formed in the substrate and being of a second doping type which is different from the first doping type; a second well region formed in the substrate, being of the second doping type, and being spaced apart from the first well region so as to define an intermediate region separating the first and second well regions from each other; a first region formed within the first well region and extending into the intermediate region between the first and second well regions, the first region being of the second doping type; a second region formed within the second well region and extending into the intermediate region between the first and second well regions, the second region being of the second doping type; and a control gate bridging over the intermediate region between the first and second regions.

摘要翻译： 一种MOS控制的横向SCR器件，包括第一掺杂类型的半导体衬底; 形成在所述衬底中并且具有不同于所述第一掺杂类型的第二掺杂类型的第一阱区; 形成在所述衬底中的第二阱区，所述第二阱区具有第二掺杂型，并且与所述第一阱区间隔开，以便限定使所述第一阱区和所述第二阱区彼此分离的中间区; 第一区域，形成在第一阱区内并延伸到第一和第二阱区之间的中间区域，第一区域是第二掺杂型; 第二区域，形成在第二阱区域内并延伸到第一和第二阱区域之间的中间区域，第二区域是第二掺杂型; 以及跨越所述第一和第二区域之间的中间区域的控制栅极。

公开(公告)号：US6002568A

公开(公告)日：1999-12-14

申请号：US106115

申请日：1998-06-29

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/00

CPC分类号： H01L27/0262 ,  H01L27/0251 ,  H01L27/0255

摘要： In this invention, a whole-chip ESD protection scheme with the SCR string or the SCR/diode-mixed string are proposed to protect the mixed-voltage CMOS IC's against the ESD damage. The SCR string or the SCR/diode-mixed string is placed between the separated power lines. The ESD current is arranged to be discharged through the SCR string or the SCR/diode-mixed string and the ESD clamps between the power lines. Therefore, the internal circuits and the interface circuits between the circuits with different power supplies can be prevented from ESD damages. The number of the SCR's or the diodes in the SCR string or the SCR/diode-mixed string connected between the different power lines is dependent on the voltage difference between the different power supplies in the mixed-voltage CMOS IC's. When the IC is in the normal operating conditions, such SCR string or the SCR/diode-mixed string between the different power lines is kept off to maintain the independence of the power supplies in the mixed-voltage COMS IC.

摘要翻译： 在本发明中，提出了具有SCR串或SCR /二极管混合串的全芯片ESD保护方案，以保护混合电压CMOS IC免受ESD损坏。 SCR串或SCR /二极管混合串放置在分离的电源线之间。 ESD电流被布置为通过SCR串或SCR /二极管混合串放电，并且ESD电源被布置成通过SCR串或电源线之间的ESD钳位放电。 因此，可以防止内部电路和具有不同电源的电路之间的接口电路免受ESD损坏。 SCR串联中的SCR或二极管数量连接在不同电源线之间的SCR /二极管混合串的数量取决于混合电压CMOS IC中不同电源之间的电压差。 当IC处于正常工作状态时，这些SCR串或不同电源线之间的SCR /二极管混合串被保持关闭，以保持混合电压COMS IC中电源的独立性。

公开(公告)号：US6144542A

公开(公告)日：2000-11-07

申请号：US210954

申请日：1998-12-15

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： In this invention, a new whole-chip ESD protection scheme with the ESD buses has been proposed to solve the ESD protection issue of the CMOS IC having a large number of separated power lines. Multiple ESD buses, which are formed by the wide metal lines, have been added into the CMOS IC having a large number of separated power lines. The bi-directional ESD-connection cells are connected between the separated power lines and the ESD buses, but not between the separated power lines. The ESD current on the CMOS IC with more separated power lines are all conducted into the ESD buses, therefore the ESD current can be conducted by the ESD buses away from the internal circuits and quickly discharged through the designed ESD protection devices to ground. By using this new whole-chip ESD protection scheme with the ESD buses, the CMOS IC having more separated power lines can be still safely protected against ESD damages.

摘要翻译： 在本发明中，已经提出了具有ESD总线的新的全芯片ESD保护方案来解决具有大量分离电力线的CMOS IC的ESD保护问题。 由宽金属线形成的多个ESD总线已经被添加到具有大量分离电力线的CMOS IC中。 双向ESD连接单元连接在分离的电源线和ESD总线之间，而不是分离的电源线之间。 具有更多分离电源线的CMOS IC上的ESD电流都被导入ESD总线，因此ESD电流可以由ESD总线远离内部电路进行，并通过设计的ESD保护器件快速放电到地。 通过使用这种新的全芯片ESD保护方案与ESD总线，具有更多分离电源线的CMOS IC可以安全地防止ESD损坏。

公开(公告)号：US6011681A

公开(公告)日：2000-01-04

申请号：US140385

申请日：1998-08-26

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0262 ,  H01L27/0251

摘要： CMOS VLSI chips with pin counts greater than 100 often have multiple power pins to supply sufficient current for circuit operations. In mixed voltage ICs there are separated power pins with different power supplies for specified power operations, and in these ICs the power supplies for the digital and analog circuits are often separated due to noise considerations. In such ICs with separated power pins, the interface circuits between the circuits with different power pins are vulnerable to ESD (electrostatic discharge) stress. Even though there are suitable ESD protection circuits around the input and output pins of the IC, unexpected ESD damage still happens to the interface circuits between the circuits with different power pins, so that a whole-chip ESD protection arrangement using bi-directional SCRs is provided to protect the CMOS ICs against ESD damage. The bi-directional SCRs are placed between the separated power lines of the CMOS IC to provide ESD current discharging paths between the separated power lines. Thus, the vulnerable internal circuits and interface circuits between the different power pins are rendered remote from the ESD damage. The present ESD protection arrangement can be applied to chips having multiple or mixed-voltage power pins.

摘要翻译： 引脚数大于100的CMOS VLSI芯片通常具有多个电源引脚，为电路操作提供足够的电流。 在混合电压IC中，具有用于指定功率操作的不同电源的分离的电源引脚，并且在这些IC中，由于噪声考虑，数字和模拟电路的电源通常是分离的。 在具有分离电源引脚的这种IC中，具有不同电源引脚的电路之间的接口电路易受ESD（静电放电）应力的影响。 即使在IC的输入和输出引脚周围有合适的ESD保护电路，但是在具有不同电源引脚的电路之间的接口电路仍然发生意外的ESD损坏，因此使用双向SCR的全芯片ESD保护装置是 用于保护CMOS IC免受ESD损坏。 将双向SCR放置在CMOS IC的分离的电源线之间，以提供分离的电力线之间的ESD电流放电路径。 因此，不同电源引脚之间的易损内部电路和接口电路远离ESD损坏。 本ESD保护装置可以应用于具有多个或混合电压电源引脚的芯片。

公开(公告)号：US5959820A

公开(公告)日：1999-09-28

申请号：US64894

申请日：1998-04-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0248

摘要： The cascode LVTSCR includes two or more SCRs (silicon controlled rectifiers). Each SCR has an anode, a control gate, and a cathode. The SCRs are cascoded in series by coupling the control gates of same type SCRs in common and coupling the cathode of one SCR to the anode of next SCR in series. The holding voltage of the cascode LVTSCR can be designed to be greater than VDD voltage level of the IC. Therefore, the cascode LVTSCR has no latchup problem in the CMOS IC's. The electrostatic discharge (ESD) protection circuit in the present invention includes a cascode LVTSCR (low-voltage triggering silicon controlled rectifier) with an anode and a cathode coupled between power supplies, and a detecting circuit coupled between the power supplies for detecting an electrostatic charge to trigger the control gates of the cascode LVTSCR for dissipating the electrostatic discharge. The ESD protection circuit including the cascode LVTSCR can sustain high ESD stress but without causing the latchup problem in the CMOS IC's.

摘要翻译： 级联LVTSCR包括两个或更多个SCR（可控硅整流器）。 每个SCR具有阳极，控制栅极和阴极。 通过将相同类型的SCR的控制栅极共同连接并将一个SCR的阴极串联连接到下一个SCR的阳极，SCR串联。 级联LVTSCR的保持电压可以设计为大于IC的VDD电压电平。 因此，串联LVTSCR在CMOS IC中没有闭锁问题。 本发明中的静电放电（ESD）保护电路包括在电源之间连接有阳极和阴极的共源共栅LVTSCR（低电压触发可控硅整流器）和耦合在用于检测静电电荷的电源之间的检测电路 以触​​发级联LVTSCR的控制栅极用于消散静电放电。 包括共源共栅LVTSCR的ESD保护电路可以承受高ESD应力，但不会导致CMOS IC的闭锁问题。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0259 ,  H01L27/0251

摘要： An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

摘要翻译： 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US07054122B2

公开(公告)日：2006-05-30

申请号：US10383424

申请日：2003-03-07

申请人： Chung-Hui Chen ,  Hun-Hsien Chang

发明人： Chung-Hui Chen ,  Hun-Hsien Chang

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention comprises an ESD clamp circuit used in an integrated circuit with plural power supply. The ESD clamp circuit, connected between core voltage source and low voltage source, is fabricated by a process which fabricates core circuit. The ESD clamp circuit has a low trigger voltage, so it can conduct large current to protect the core circuit before the core circuit is damaged.