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公开(公告)号:US20220028620A1
公开(公告)日:2022-01-27
申请号:US17498872
申请日:2021-10-12
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Akihiro Tsuru , Kazuhisa Uchida
IPC: H01G4/30 , C04B35/468 , H01G4/12 , H01G4/012 , H01G2/02
Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.
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公开(公告)号:US12165810B2
公开(公告)日:2024-12-10
申请号:US18233407
申请日:2023-08-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Kazuhisa Uchida
Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
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公开(公告)号:US11776751B2
公开(公告)日:2023-10-03
申请号:US17591628
申请日:2022-02-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yoshiyuki Abe , Kazuhisa Uchida
CPC classification number: H01G4/1227 , H01G4/0085 , H01G4/2325 , H01G4/30
Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
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公开(公告)号:US11443895B2
公开(公告)日:2022-09-13
申请号:US16822068
申请日:2020-03-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Akitaka Doi , Akito Mori , Kazuhisa Uchida
Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.
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公开(公告)号:US20200303125A1
公开(公告)日:2020-09-24
申请号:US16818261
申请日:2020-03-13
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Akihiro Tsuru , Kazuhisa Uchida
IPC: H01G4/30 , H01G4/012 , H01G4/12 , H01G2/02 , C04B35/468
Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.
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公开(公告)号:US20200185152A1
公开(公告)日:2020-06-11
申请号:US16693678
申请日:2019-11-25
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Kazuhisa Uchida , Naoto Muranishi
Abstract: A multilayer ceramic capacitor that includes outer electrodes and a multilayer body having stacked inner electrode layers and dielectric layers. The dielectric layers in an effective section contain, relative to 100 parts by mole of Ti, 0.7 to 1.2 parts by mole of Si, 0.9 to 1.1 parts by mole of Dy, 0.24 to 0.34 parts by mole of Mg, 0.17 to 0.23 parts by mole of Al, 0.09 to 0.11 parts by mole of Mn, and 0.04 to 0.06 parts by mole of V. The dielectric layers have a Ba/Ti molar ratio of 1.0073 to 1.0083.
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