Multilayer ceramic capacitor
    1.
    发明授权

    公开(公告)号:US11776751B2

    公开(公告)日:2023-10-03

    申请号:US17591628

    申请日:2022-02-03

    CPC classification number: H01G4/1227 H01G4/0085 H01G4/2325 H01G4/30

    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.

    Multilayer ceramic capacitor
    2.
    发明授权

    公开(公告)号:US11972900B2

    公开(公告)日:2024-04-30

    申请号:US17668411

    申请日:2022-02-10

    Inventor: Yoshiyuki Abe

    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, first and second main surfaces opposing each other in a lamination direction, first and second end surfaces opposing each other in a length direction which intersects the lamination direction, and first and second side surfaces opposing each other in a width direction which intersects the lamination direction and the length direction, and external electrodes on the first and second end surfaces, and each electrically connected to the internal electrode layers, wherein the multilayer body includes a slit in at least one of the first side surface, the second side surface, and the second main surface defining and functioning as a board-mounting surface.

    Mounting structure of electronic component

    公开(公告)号:US12267956B2

    公开(公告)日:2025-04-01

    申请号:US17955795

    申请日:2022-09-29

    Abstract: A mounting structure of an electronic component includes a multilayer ceramic capacitor including lands on a board and spaced apart from each other, solder on the lands, and a component main body including external electrodes on both end portions of the component main body in a length direction, each of the pair of external electrodes being connected to a corresponding one of the pair of lands via the solder. When a separation direction of the lands is an X direction and a direction orthogonal or substantially orthogonal to the X direction is a Y direction, when a width dimension of the land along the Y direction is c, a dimension of each of the external electrodes in the X direction is e, and a gap between the land and the external electrode is Gap, 3.4

    Multilayer ceramic capacitor
    4.
    发明授权

    公开(公告)号:US12100555B2

    公开(公告)日:2024-09-24

    申请号:US18237505

    申请日:2023-08-24

    CPC classification number: H01G4/1227 H01G4/0085 H01G4/2325 H01G4/30

    Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.

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