公开(公告)号：US20220028620A1

公开(公告)日：2022-01-27

申请号：US17498872

申请日：2021-10-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akihiro Tsuru ,  Kazuhisa Uchida

IPC: H01G4/30 ,  C04B35/468 ,  H01G4/12 ,  H01G4/012 ,  H01G2/02

Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.

公开(公告)号：US20180158610A1

公开(公告)日：2018-06-07

申请号：US15888351

申请日：2018-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： NORIYUKI INOUE ,  Takeo Arakawa ,  Kensuke Aoki ,  Hiromasa Saeki ,  Koichi Kanryo ,  Akihiro Tsuru ,  Haruhiko Mori

IPC: H01G4/06 ,  H01G4/30

Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.

公开(公告)号：US12080484B2

公开(公告)日：2024-09-03

申请号：US17498872

申请日：2021-10-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akihiro Tsuru ,  Kazuhisa Uchida

IPC: C04B35/468 ,  H01G2/02 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/30 ,  C04B35/4682 ,  H01G2/02 ,  H01G4/012 ,  H01G4/1227

Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.

公开(公告)号：US12020867B2

公开(公告)日：2024-06-25

申请号：US18110396

申请日：2023-02-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Hideaki Tanaka ,  Masahiro Wakashima ,  Daisuke Hamada ,  Hironori Tsutsumi ,  Satoshi Maeno ,  Ryota Aso ,  Koji Moriyama ,  Akihiro Tsuru

IPC: H01G4/12 ,  H01G4/008 ,  H01G4/012 ,  H01G4/224 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G4/1227 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/224 ,  H01G4/2325 ,  H01G4/30

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

公开(公告)号：US11264174B2

公开(公告)日：2022-03-01

申请号：US16818261

申请日：2020-03-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akihiro Tsuru ,  Kazuhisa Uchida

IPC: C04B35/468 ,  H01G2/02 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.

公开(公告)号：US09959973B2

公开(公告)日：2018-05-01

申请号：US14853088

申请日：2015-09-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshito Saito ,  Yasuhiro Nishisaka ,  Makoto Ogawa ,  Akihiro Tsuru

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/008 ,  H01G4/12

CPC classification number: H01G4/2325 ,  H01G4/0085 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor that includes a layered body in which dielectric layers and internal electrode layers are layered alternately, an external electrode on a surface of the layered body and a plating layer on a surface of the external electrode. The external electrode contains Cu, and a protective layer containing Cu2O is provided at a joining portion between the external electrode and the plating layer. When heat is applied to the layered body after the external electrode is removed, a ratio of an arithmetic mean value Xa of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 350° C. with respect to an arithmetic mean value Y of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 230° C. and lower than or equal to 250° C. (Xa/Y) is less than or equal to 0.66.

公开(公告)号：US11532438B2

公开(公告)日：2022-12-20

申请号：US16930350

申请日：2020-07-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takehisa Sasabayashi ,  Kiyoshiro Ishibe ,  Kenji Ueno ,  Ai Fukumori ,  Akihiro Tsuru ,  Daisuke Hamada

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/248 ,  H01G4/012

Abstract: A multilayer electronic component includes a multilayer body including dielectric layers and inner electrode layers. Each of the dielectric layers includes first crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 300 nm and an average aspect ratio of more than or equal to about 5, each of the inner electrode layers includes second crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 150 nm and an average aspect ratio of more than or equal to about 5, where an aspect ratio is represented by a ratio of a major axis of each plate-shaped object to a thickness of the plate-shaped object with the major axis of the plate-shaped object being orthogonal or substantially orthogonal to a thickness direction of the plate-shaped object.

公开(公告)号：US10546691B2

公开(公告)日：2020-01-28

申请号：US15888351

申请日：2018-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noriyuki Inoue ,  Takeo Arakawa ,  Kensuke Aoki ,  Hiromasa Saeki ,  Koichi Kanryo ,  Akihiro Tsuru ,  Haruhiko Mori

IPC: H01G4/30 ,  H01G4/06

Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.

公开(公告)号：US09928960B2

公开(公告)日：2018-03-27

申请号：US14744123

申请日：2015-06-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toru Nakanishi ,  Toshihiro Okamatsu ,  Akihiro Tsuru ,  Hiroyuki Wada

IPC: C04B35/468 ,  H01G4/12 ,  H01G4/30 ,  H01G4/01 ,  H01G4/224 ,  H01G4/008

CPC classification number: H01G4/30 ,  C04B35/4682 ,  C04B2235/3206 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3244 ,  C04B2235/3262 ,  C04B2235/3418 ,  C04B2235/79 ,  H01G4/0085 ,  H01G4/01 ,  H01G4/1227 ,  H01G4/1245 ,  H01G4/224

Abstract: A monolithic ceramic capacitor that contains a perovskite compound including Ba and Ti and at least one type of element selected from Gd, Tb, and Dy, and contains elements selected from Y, Si, Mn, Mg, and Zr. The content a of at least one element selected from Gd, Tb, and Dy satisfies 0.2≤a≤0.8, the content b of Y satisfies 0.0≤b≤0.5, the content c of Si satisfies 0.0≤c≤2.5, the content d of Mn satisfies 0.0≤d≤0.25, the content e of Mg satisfies 0.0≤e≤1.2, the content f of Zr satisfies 0.0≤f≤0.5, and the molar ratio m of the content of Ba/(f+the content of Ti) satisfies 0.99≤m≤1.01, where the total content of Ti is 100 parts by mole.

公开(公告)号：US20160086733A1

公开(公告)日：2016-03-24

申请号：US14853088

申请日：2015-09-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshito Saito ,  Yasuhiro Nishisaka ,  Makoto Ogawa ,  Akihiro Tsuru

IPC: H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/2325 ,  H01G4/0085 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor that includes a layered body in which dielectric layers and internal electrode layers are layered alternately, an external electrode on a surface of the layered body and a plating layer on a surface of the external electrode. The external electrode contains Cu, and a protective layer containing Cu2O is provided at a joining portion between the external electrode and the plating layer. When heat is applied to the layered body after the external electrode is removed, a ratio of an arithmetic mean value Xa of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 350° C. with respect to an arithmetic mean value Y of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 230° C. and lower than or equal to 250° C. (Xa/Y) is less than or equal to 0.66.

Abstract translation: 一种层叠陶瓷电容器，其包括交替层叠电介质层和内部电极层的层叠体，层叠体的表面上的外部电极和外部电极的表面上的镀层。 外部电极含有Cu，在外部电极和镀层之间的接合部分设置有含有Cu2O的保护层。 当在除去外部电极之后对层叠体施加热量时，相对于算术平均值，在单位温度下产生的氢的量的算术平均值Xa在高于或等于350℃的范围内 在高于或等于230℃且低于或等于250℃的范围内每单位温度产生的氢气量的值Y（Xa / Y）小于或等于0.66。