-
公开(公告)号：US5157286A
公开(公告)日：1992-10-20
申请号：US484144
申请日：1990-02-23
CPC分类号： G01R31/318558 , G01R31/318552 , G06F1/10 , G11C19/00
摘要： A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in response to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
摘要翻译： 呈现包括多个寄存器30,39的逻辑电路; 每个寄存器30具有第一寄存器锁存器31,41，用于响应于第一时钟信号37将数据计时到寄存器30中;以及第二寄存器锁存器，用于响应于第二时钟信号38将数据输出寄存器;以及组合逻辑包括地址 用于将数据寻址到寄存器的逻辑4和用于响应于地址逻辑禁止输入到寄存器的第一时钟信号的第一抑制逻辑33，其中逻辑电路还包括第二抑制逻辑34,35，用于禁止第二时钟信号输入 该寄存器集中响应地址逻辑和第一个时钟信号。
-
公开(公告)号：US4910687A
公开(公告)日：1990-03-20
申请号：US116104
申请日：1987-11-03
CPC分类号： G09G5/395
摘要： Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, with each data group corresponding to a respective value for a pixel in an image, wherein the bit-length of the pixel value is selectable. The apparatus includes a gate circuit having 2.sup.M parallel input junctions connected to the outputs of the memory and 2.sup.N output junctions. The gate circuit selectively converts each set of 2.sup.M parallel inputs at the input junctions in to 2.sup.M-n successive data groups, with each group having a bit-length of 2.sup.n bits. Each such group is transmitted to 2.sup.n of the 2.sup.N output junctions. A communication element conveys to the gate circuit a signal which controls the bit-length 2.sup.n of the data groups, wherein n is an integer 1.ltoreq.n.ltoreq.N.ltoreq.M.
-
搜索结果
12 条记录 (耗时 0.015 秒)
