公开(公告)号：US20060075012A1

公开(公告)日：2006-04-06

申请号：US11238123

申请日：2005-09-28

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: G06F7/38

CPC classification number: G06F7/57 ,  G06F15/7867

Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.

Abstract translation: 使用一个或多个计算块，每个块具有乘法器，累加器和多路复用器的现场可编程门阵列（FPGA）中的DSP功能的有效实现。 该结构以快速和高度紧凑的方式实现了大多数常见DSP方程。 提供了一种利用专用DSP线路级联这些块的新颖方法，这导致了n阶段MAC操作的非常简单和精通的实现。

公开(公告)号：US07755387B2

公开(公告)日：2010-07-13

申请号：US11264674

申请日：2005-11-01

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: H01L25/00

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.

Abstract translation: 具有直接互连结构的改进的FPGA，以提供选择性数据路由，而不强调通用路由资源并且实现FPGA内的高速率的数据交换。 至少两个IP内核通过直接互连结构相互连接，以实现IP内核的端口之间的数据交互，并在IP内核之间提供可配置的总线宽度路由，以及连接到IP内核的多个逻辑块 通过直接互连结构来实现IP核和多个逻辑块之间的同时数据路由。

公开(公告)号：US07750673B2

公开(公告)日：2010-07-06

申请号：US11261420

申请日：2005-10-27

Applicant: Manuj Ayodhyawasi ,  Kailash Digari

Inventor： Manuj Ayodhyawasi ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each set having predetermined number of input lines; an equal number of sets of routing lines, each set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.

Abstract translation: 可编程设备中的改进的互连结构为路由架构提供了一个新的维度，其中架构分为多个域。 它包括至少一组输入线，每组输入线具有预定数量的输入线; 相同数量的路由线路组，每组路由线路使用开关盒连接到相应的一组输入线路; 从而形成基于域的路由结构，每个域与其他域不相交。 完成将FPGA路由资源分离成各种独立的路由域; 每个域提供连接以将信号路由到一组接收器。

公开(公告)号：US20100097099A1

公开(公告)日：2010-04-22

申请号：US12645236

申请日：2009-12-22

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

Abstract translation: 一种FPGA，包括用于提供选择性数据路由的直接互连结构，而不强调通用路由资源并且实现FPGA内的高速数据交换。 至少两个IP核通过所述直接互连结构相互连接，以便能够在所述IP核的端口之间同时进行数据交互，并且用于在所述IP核之间提供可配置的总线宽度路由，以及连接到所述IP核的多个逻辑块 通过所述直接互连结构来实现在所述IP核和所述多个逻辑块之间的同时数据路由。

公开(公告)号：US20060087342A1

公开(公告)日：2006-04-27

申请号：US11261420

申请日：2005-10-27

Applicant: Manuj Ayodhyawasi ,  Kailash Digari

Inventor： Manuj Ayodhyawasi ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each said set having predetermined number of input lines; an equal number of sets of routing lines, each said set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.

Abstract translation: 可编程设备中的改进的互连结构为路由架构提供了一个新的维度，其中架构分为多个域。 它包括至少一组输入线，每组输入线具有预定数量的输入线; 相同数量的路由线路组，每条所述路由线路组使用开关盒连接到相应的一组输入线路; 从而形成基于域的路由结构，每个域与其他域不相交。 完成将FPGA路由资源分离成各种独立的路由域; 每个域提供连接以将信号路由到一组接收器。