公开(公告)号：US20080259706A1

公开(公告)日：2008-10-23

申请号：US12078743

申请日：2008-04-04

申请人： Norihiko Sumitani ,  Hidenari Kanehara

发明人： Norihiko Sumitani ,  Hidenari Kanehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C7/14

摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.

摘要翻译： 半导体存储器包括：第一和第二位线; 预充电电路，用于将第一和第二位线预充电到预定电位; 每个连接到第一或第二位线的多个存储单元，所选择的一个存储器单元根据所选择的存储单元保持的信号维持或放电预充电的第一和第二位线之一; 用于选择存储单元的字线; 分别连接到第一和第二位线的第一和第二参考单元，第一和第二参考单元中选定的一个放电连接到所选参考单元的第一或第二位线; 以及分别用于选择第一和第二参考单元的第一和第二参考单元格字线。

公开(公告)号：US07366037B2

公开(公告)日：2008-04-29

申请号：US11449606

申请日：2006-06-09

申请人： Norihiko Sumitani ,  Hidenari Kanehara

发明人： Norihiko Sumitani ,  Hidenari Kanehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C7/14

摘要： A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.

公开(公告)号：US20090067273A1

公开(公告)日：2009-03-12

申请号：US12201384

申请日：2008-08-29

申请人： Tsuyoshi KOIKE ,  Hidenari Kanehara

发明人： Tsuyoshi KOIKE ,  Hidenari Kanehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413

摘要： A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

摘要翻译： 连接到存储单元的位线的电压通过预充电电路升高到电源电压。 在从存储单元读取数据之前，通过降压电路将位线的电压降低到低于电源电压的电压电平。 预充电开关元件控制高电位侧电源和预充电电路之间的连接以及低电位侧电源与预充电电路之间的连接。 在预充电开关元件和高电位侧电源之间设置电源连接电路。 在预充电开关元件连接到电源连接电路的连接点和低电位侧电源之间设置有接地连接电路。

公开(公告)号：US07023722B2

公开(公告)日：2006-04-04

申请号：US10737799

申请日：2003-12-18

申请人： Hidenari Kanehara ,  Hiroaki Okuyama

发明人： Hidenari Kanehara ,  Hiroaki Okuyama

IPC分类号： G11C11/00

CPC分类号： G11C11/419

摘要： The respective sources of drive transistors included in memory cells that are located in each of multiple columns and connected to a corresponding one of bit line pairs are connected commonly to a low voltage power supply VSS via an assertion transistor. When data is written, the assertion transistor for the memory cells connected to a selected one of the bit line pairs and located in the identical column is negated, so that the sources of the drive transistors in the memory cells in that column are allowed to float. Consequently, even with a low power supply voltage, it is possible to write the data into a single selected memory cell, while data in the unselected memory cells can be retained favorably.

摘要翻译： 包括在存储单元中的驱动晶体管的源极位于多列中的每一个并连接到相应的一对位线对中的驱动晶体管的源极通过断言晶体管共同连接到低电压电源VSS。 当写入数据时，与连接到选定的一个位线对并位于相同列中的存储器单元的断言晶体管被否定，使得该列中的存储单元中的驱动晶体管的源极被允许浮动 。 因此，即使使用低电源电压，也可以将数据写入单个选择的存储单元中，同时可以有利地保留未选择的存储单元中的数据。

公开(公告)号：US20110211408A1

公开(公告)日：2011-09-01

申请号：US13104501

申请日：2011-05-10

申请人： Tsuyoshi KOIKE ,  Hidenari Kanehara

发明人： Tsuyoshi KOIKE ,  Hidenari Kanehara

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C11/413

摘要： A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

摘要翻译： 连接到存储单元的位线的电压通过预充电电路升高到电源电压。 在从存储单元读取数据之前，通过降压电路将位线的电压降低到低于电源电压的电压电平。 预充电开关元件控制高电位侧电源和预充电电路之间的连接以及低电位侧电源与预充电电路之间的连接。 在预充电开关元件和高电位侧电源之间设置电源连接电路。 在预充电开关元件连接到电源连接电路的连接点和低电位侧电源之间设置有接地连接电路。

公开(公告)号：US07965569B2

公开(公告)日：2011-06-21

申请号：US12201384

申请日：2008-08-29

申请人： Tsuyoshi Koike ,  Hidenari Kanehara

发明人： Tsuyoshi Koike ,  Hidenari Kanehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413

摘要： A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

摘要翻译： 连接到存储单元的位线的电压通过预充电电路升高到电源电压。 在从存储单元读取数据之前，通过降压电路将位线的电压降低到低于电源电压的电压电平。 预充电开关元件控制高电位侧电源和预充电电路之间的连接以及低电位侧电源与预充电电路之间的连接。 在预充电开关元件和高电位侧电源之间设置电源连接电路。 在预充电开关元件连接到电源连接电路的连接点和低电位侧电源之间设置有接地连接电路。

公开(公告)号：US20060262635A1

公开(公告)日：2006-11-23

申请号：US11435725

申请日：2006-05-18

申请人： Hidenari Kanehara

发明人： Hidenari Kanehara

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.

摘要翻译： 一种半导体存储器件，其能够在不增加正常电压下的字线激活周期的情况下以较低的电压进行高速写入操作。 存储器件具有写入电路，该写入电路包括分别具有连接到地电位的源的两个NMOS晶体管。 一个晶体管具有连接到一对位线中的一个的漏极，而另一个晶体管具有连接到另一位线的漏极。 存储器件还具有列选择和数据输入电路，其生成要写入的数据的反相数据和写列选择信号的逻辑积，将逻辑积输入到一个晶体管的栅极，生成逻辑积 要写入的数据和写入列选择信号，并将逻辑积输入到另一个晶体管的栅极。

公开(公告)号：US07366007B2

公开(公告)日：2008-04-29

申请号：US11435725

申请日：2006-05-18

申请人： Hidenari Kanehara

发明人： Hidenari Kanehara

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.

摘要翻译： 一种半导体存储器件，其能够在不增加正常电压下的字线激活周期的情况下以较低的电压进行高速写入操作。 存储器件具有写入电路，该写入电路包括分别具有连接到地电位的源的两个NMOS晶体管。 一个晶体管具有连接到一对位线中的一个的漏极，而另一个晶体管具有连接到另一位线的漏极。 存储器件还具有列选择和数据输入电路，其生成要写入的数据的反相数据和写列选择信号的逻辑积，将逻辑积输入到一个晶体管的栅极，生成逻辑积 要写入的数据和写入列选择信号，并将逻辑积输入到另一个晶体管的栅极。

公开(公告)号：US07978503B2

公开(公告)日：2011-07-12

申请号：US11730977

申请日：2007-04-05

申请人： Tsuyoshi Koike ,  Hidenari Kanehara

发明人： Tsuyoshi Koike ,  Hidenari Kanehara

IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C11/417

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.

摘要翻译： 提供用于检测写入完成定时的伪存储单元作为存储单元的副本。 当通过电源控制和存储单元的基板电位控制来协助写入操作时，结束写入辅助操作的定时由电压控制电路基于关于虚拟存储单元的信息来确定。 例如，电压控制电路在存储单元中的数据写入操作中执行使用下拉晶体管降低分配给P沟道MOS负载晶体管的源极电源的电压的写入辅助操作。 此后，当检测到虚拟存储单元中的数据写入操作完成时，电压控制电路结束写入辅助操作，并且使用上拉晶体管将源极电源的电压恢复到原始电平。

公开(公告)号：US20070263447A1

公开(公告)日：2007-11-15

申请号：US11730977

申请日：2007-04-05

申请人： Tsuyoshi Koike ,  Hidenari Kanehara

发明人： Tsuyoshi Koike ,  Hidenari Kanehara

IPC分类号： G11C16/04

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.

摘要翻译： 提供用于检测写入完成定时的伪存储单元作为存储单元的副本。 当通过电源控制和存储单元的基板电位控制来协助写入操作时，结束写入辅助操作的定时由电压控制电路基于关于虚拟存储单元的信息来确定。 例如，电压控制电路在存储单元中的数据写入操作中执行使用下拉晶体管降低分配给P沟道MOS负载晶体管的源极电源的电压的写入辅助操作。 此后，当检测到虚拟存储单元中的数据写入操作完成时，电压控制电路结束写入辅助操作，并且使用上拉晶体管将源极电源的电压恢复到原始电平。