公开(公告)号：US20220201323A1

公开(公告)日：2022-06-23

申请号：US17476947

申请日：2021-09-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Takashi HASHIMOTO

IPC: H04N19/513 ,  H04N19/159 ,  H04N19/186 ,  H04N19/182

Abstract: Provided is an encoder that achieves further improvement. The encoder includes processing circuitry and memory. Using the memory, the processing circuitry: obtains two prediction images from two reference pictures; derives a luminance gradient value of each pixel position in each of the two prediction images; derives a luminance local motion estimation value of each pixel position in a current block; generates a luminance final prediction image using a luminance value and the luminance gradient value in each of the two prediction images, and the luminance local motion estimation value of the current block; and generates a chrominance final prediction image using at least one of the luminance gradient value of each of the two prediction images or the luminance local motion estimation value of the current block, and chrominance of each of the two prediction images.

公开(公告)号：US20210152842A1

公开(公告)日：2021-05-20

申请号：US17130298

申请日：2020-12-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US20200053386A1

公开(公告)日：2020-02-13

申请号：US16654668

申请日：2019-10-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/573 ,  H04N19/52 ,  H04N19/176

Abstract: An encoder includes memory and circuitry. The circuitry (i) encodes first control information indicating one mode, (ii) encodes second control information indicating whether it is possible to perform the motion compensation in a unit of a sub-block, (iii) derives the motion vector of the block in the one mode, (iv) determines whether to perform the motion compensation in the unit of the sub-block or the motion compensation in a unit of the block, (v) derives a motion vector of the sub-block and performs the motion compensation in the unit of the sub-block using the motion vector of the sub-block when determining to perform the motion compensation in the unit of the sub-block, and (vi) performs the motion compensation in the unit of the block using the motion vector of the block when determining to perform the motion compensation in the unit of the block.

公开(公告)号：US20250056034A1

公开(公告)日：2025-02-13

申请号：US18931329

申请日：2024-10-30

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US20240048755A1

公开(公告)日：2024-02-08

申请号：US18489684

申请日：2023-10-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/176 ,  H04N19/59

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/176 ,  H04N19/59

Abstract: An encoder that; obtains two prediction images by performing motion compensation using two motion vectors; obtains a gradient value of each of pixels included in the two prediction images; derives a local motion estimation value for each of sub-blocks based on the pixel value and the gradient value of each of the pixels, the sub-blocks being obtained by partitioning the current block; and generates a final prediction image for the current block using the pixel value and the gradient value of each of the pixels, and the local motion estimation value derived for each of the sub-blocks. Each of the pixels in the two prediction images is interpolated with sub-pixel accuracy, and a reference range for the interpolation is included in a normal reference range that is referred to for motion compensation for the current block in normal inter prediction performed without using the local motion estimation value.

公开(公告)号：US20230232034A1

公开(公告)日：2023-07-20

申请号：US18125816

申请日：2023-03-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

CPC classification number: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US20200329243A1

公开(公告)日：2020-10-15

申请号：US16911834

申请日：2020-06-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Takashi HASHIMOTO ,  Tadamasa TOMA

IPC: H04N19/122 ,  H04N19/13 ,  H04N19/146 ,  H04N19/176 ,  H04N19/18

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of one or more basic blocks in a frequency transform block, according to a conversion table, to encode the image information which includes the data value. When binarizing the data value, the circuitry selects the conversion table from a plurality of tables including two or more tables which differ from each other in difference between a longest bit length and a shortest bit length of a plurality of binary values associated with a plurality of data values, according to the position of the current basic block in the current frequency transform block which is the frequency transform block including the current basic block, and binarizes the data value according to the conversion table selected.

公开(公告)号：US20200213613A1

公开(公告)日：2020-07-02

申请号：US16816733

申请日：2020-03-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI ,  Ryuichi KANOH

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes: circuitry; and memory, in which using the memory, the circuitry, in affine motion compensation prediction in inter prediction for a current block, places a limit on a range within which motion estimation or motion compensation is performed, and performs the motion compensation for the current block.

公开(公告)号：US20190174133A1

公开(公告)日：2019-06-06

申请号：US16269134

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/13 ,  H04N19/157

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of basic blocks in a frequency transform block composed of a plurality of frequency transform coefficients, according to a conversion table in which data values and binary values are associated with each other, to encode the image information which includes the data value. When binarizing the data value, the circuitry (160) selects the conversion table from tables including a first table which includes association with a data value indicating 0 as the number of non-zero coefficients and a second table which does not include association with a data value indicating 0 as the number of non-zero coefficients, and binarizes the data value according to the conversion table selected.

公开(公告)号：US20240333967A1

公开(公告)日：2024-10-03

申请号：US18743382

申请日：2024-06-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.