公开(公告)号：US06670229B2

公开(公告)日：2003-12-30

申请号：US10077288

申请日：2002-02-15

申请人： Loris Vendrame ,  Paolo Ghezzi

发明人： Loris Vendrame ,  Paolo Ghezzi

IPC分类号： H01L218238

CPC分类号： H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

摘要： A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 1016 and 1017 atoms/cm3.

摘要翻译： 双极晶体管是通过制造CMOS非易失性存储器件的工艺生产的，并且是集成电路的一部分。 集成电路包括具有第一导电类型的半导体衬底，形成在所述衬底中的PMOS晶体管，形成在所述衬底中的NMOS晶体管和双极晶体管。 所述双极晶体管包括：具有从所述双极晶体管的表面设置在规定深度的第二导电类型的掩埋半导体层，具有与所述掩埋半导体层直接接触的第二导电类型的隔离半导体区域， 用于限定所述衬底的一部分，形成基部区域; 形成在具有第二导电类型的所述基极区内的发射极区域，形成在具有第一导电类型的所述基极区域内的所述晶体管的基极接触区域，形成在具有第二导电类型的所述隔离半导体区域内的集电极接触区域 ，其中所述碱性区具有10 16和10 17个原子/ cm 3之间的掺杂浓度。

公开(公告)号：US5600590A

公开(公告)日：1997-02-04

申请号：US477302

申请日：1995-06-07

申请人： Paolo Ghezzi ,  Alfonso Maurelli

发明人： Paolo Ghezzi ,  Alfonso Maurelli

IPC分类号： H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866 ,  G11C13/00

CPC分类号： H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

摘要： A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.

摘要翻译： 一种用于在快速EEPROM存储器件中制造集成式限压器和稳定器部件的方法包括在单晶硅衬底上形成N型轻掺杂阱的步骤; 在所述N型井的表面上形成活性区的步骤; 在所述有源区上生长薄栅氧化层的步骤; 将第一重剂量的N型掺杂剂注入到所述N型阱中以获得N型区域的步骤; 向所述N型区域注入高于所述第一重剂量的N型掺杂剂的第二重剂量以获得N型阱和所述N型区域的N +接触区域的步骤; 将高于所述第一重剂量的P型掺杂剂的第三重剂量植入所述N型区域以形成P +区域的步骤。

公开(公告)号：US5486486A

公开(公告)日：1996-01-23

申请号：US301792

申请日：1994-09-07

申请人： Paolo Ghezzi ,  Alfonso Maurelli

发明人： Paolo Ghezzi ,  Alfonso Maurelli

IPC分类号： H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

CPC分类号： H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

摘要： A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+ contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.

摘要翻译： 一种用于在快速EEPROM存储器件中制造集成式限压器和稳定器部件的方法包括在单晶硅衬底上形成N型轻掺杂阱的步骤; 在所述N型井的表面上形成活性区的步骤; 在所述有源区上生长薄栅氧化层的步骤; 将第一重剂量的N型掺杂剂注入到所述N型阱中以获得N型区域的步骤; 向所述N型区域注入高于所述第一重剂量的N型掺杂剂的第二重剂量以获得N型阱和所述N型区域的N +接触区域的步骤; 将高于所述第一重剂量的P型掺杂剂的第三重剂量植入所述N型区域以形成P +区域的步骤。