公开(公告)号：US6035244A

公开(公告)日：2000-03-07

申请号：US955773

申请日：1997-10-22

申请人： Ming Chun Chen ,  Paul J. Steffan

发明人： Ming Chun Chen ,  Paul J. Steffan

IPC分类号： G06F11/22 ,  G06F19/00

CPC分类号： G06F11/2268

摘要： A defect management system with a method to update a database with defect data concerning propagator defect data. Defect data obtained from each layer formed on a semiconductor wafer is stored in a relational database. Defect data determined in a current layer to be defect data for a defect observed in a previous layer is defined as data concerning a propagator defect. Propagator defect data is used to update the data in the database relating to the previous layer.

摘要翻译： 一种缺陷管理系统，其具有使用关于传播缺陷数据的缺陷数据来更新数据库的方法。 从形成在半导体晶片上的每个层获得的缺陷数据存储在关系数据库中。 将在当前层中确定的缺陷数据作为在先前层中观察到的缺陷的缺陷数据定义为关于传播缺陷的数据。 传播者缺陷数据用于更新与上一层相关的数据库中的数据。

公开(公告)号：US5866437A

公开(公告)日：1999-02-02

申请号：US985566

申请日：1997-12-05

申请人： Ming Chun Chen ,  Paul J. Steffan

发明人： Ming Chun Chen ,  Paul J. Steffan

IPC分类号： G03F7/20 ,  H01L21/66

CPC分类号： G03F7/70625 ,  H01L22/20

摘要： A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.

摘要翻译： 使用模拟工具制造半导体晶片以确定预测的晶片电测试测量的方法。 该仿真工具结合了在当前批次上运行的先前工艺中的在线关键尺寸，以及从当前批次运行的工艺之后的工艺数据和从预测的晶片电路的比较获得的校准模拟数据 测试测量和从以前的实际晶圆电气测试测量取得的晶圆电气测试测量结果。

公开(公告)号：US06185511B2

公开(公告)日：2001-02-06

申请号：US08979629

申请日：1997-11-28

申请人： Paul J. Steffan ,  Ming Chun Chen

发明人： Paul J. Steffan ,  Ming Chun Chen

IPC分类号： G06F1900

CPC分类号： G06K9/00 ,  G06T7/0004 ,  G06T2207/30148 ,  H01L22/20

摘要： A method of determining classification codes for defects occurring in semiconductor processes comparing images of defects from a first selected wafer with images of defects in a first image reference library. The images in the first image reference library are updated from a master image reference library. The images in the master image reference library are the best images of defect types. The images in the master image reference library are in a format readable by all review stations utilized to review the images of the defect.

摘要翻译： 确定在半导体工艺中发生的缺陷的分类代码的方法，其将来自第一选定晶片的缺陷图像与第一图像参考库中的缺陷图像进行比较。 第一图像参考库中的图像从主图像参考库更新。 主图像参考库中的图像是缺陷类型的最佳图像。 主图像参考库中的图像具有可用于审查缺陷图像的所有检查站的格式。

公开(公告)号：US6011619A

公开(公告)日：2000-01-04

申请号：US987736

申请日：1997-12-09

申请人： Paul J. Steffan ,  Bryan Tracy ,  Ming Chun Chen

发明人： Paul J. Steffan ,  Bryan Tracy ,  Ming Chun Chen

IPC分类号： G01N21/956 ,  G01N21/88

CPC分类号： G01N21/95607

摘要： A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed. The optical scanning would proceed to the next swath determining its defect and continuing in such a manner until the wafer is completely scanned.

摘要翻译： 公开了一种用于确定半导体晶片上的缺陷的半导体晶片光学扫描系统和方法。 用于确定晶片缺陷的方法基于条带上的最大允许缺陷，而不是基于晶片的最大允许缺陷。 方法步骤包括根据正在使用的光学扫描设备的能力和正在测试缺陷的特定半导体晶片的能力，确定基于配方设置的单个条带的扫描区域。 预定的条带区域与由用户确定的最大允许缺陷密度一起提供并存储在光学扫描系统中。 通过将条纹的预定最大允许缺陷用作极限，可以在整个晶片上进行缺陷分析。 光学扫描系统将停止获取当达到缺陷限制时所分析的当前条带的缺陷，或直到条带缺陷分析完成。 光学扫描将进行到下一个条纹以确定其缺陷并以这种方式继续，直到晶片被完全扫描。

公开(公告)号：US07251793B1

公开(公告)日：2007-07-31

申请号：US10770711

申请日：2004-02-02

申请人： Paul J. Steffan

发明人： Paul J. Steffan

IPC分类号： G06F17/50

CPC分类号： H01L22/14

摘要： A method for facilitating semiconductor wafer lot disposition includes providing detailed descriptive information of the semiconductor wafer layout and generating data concerning at least one defect in the semiconductor wafers at an intermediate processing stage. At least one layer model is generated from the information and data to disclose the effects of the defect upon at least one later layer of the semiconductor wafers. The layer model is utilized to determine the subsequent disposition of the wafer lot.

摘要翻译： 一种用于促进半导体晶片批次布置的方法包括提供半导体晶片布局的详细描述信息，并在中间处理阶段产生关于半导体晶片中的至少一个缺陷的数据。 从信息和数据生成至少一个层模型，以将缺陷的影响公开在半导体晶片的至少一个较后层上。 层模型用于确定晶片批次的后续配置。

公开(公告)号：US06433371B1

公开(公告)日：2002-08-13

申请号：US09493428

申请日：2000-01-29

申请人： Thomas C. Scholer ,  Allen S. Yu ,  Paul J. Steffan

发明人： Thomas C. Scholer ,  Allen S. Yu ,  Paul J. Steffan

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

摘要翻译： 提供了超大规模CMOS集成电路半导体器件，其具有具有LDD结构的宽度和轮廓控制的倒梯形门，其具有逐渐的掺杂分布并且用于接触。 通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成反向梯形栅极沟槽，在衬底上的反向梯形栅极沟槽中沉积栅极电介质，形成衬底上的结构，从而形成 在反向梯形栅极沟槽中的多晶硅栅极，去除栅极层和阻挡层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结，以及制备源极/漏极延伸结和 导电连接门。

公开(公告)号：US06430572B1

公开(公告)日：2002-08-06

申请号：US09264362

申请日：1999-03-08

申请人： Paul J. Steffan ,  Allen S. Yu

发明人： Paul J. Steffan ,  Allen S. Yu

IPC分类号： G06F1730

CPC分类号： G06F17/30289 ,  G06F17/30371 ,  Y10S707/99945 ,  Y10S707/99948

摘要： A scan tool recipe management database system for recipes utilized in the scanning of semiconductor wafers during the manufacture of the semiconductor wafers. The scan tool recipe management database system includes workstations at each scan tool for simultaneously inputting recipes and changes to the recipes to the scan tool and to a scan tool recipe database.

摘要翻译： 一种扫描工具配方管理数据库系统，用于在制造半导体晶片期间在半导体晶片的扫描中使用的配方。 扫描工具配方管理数据库系统包括每个扫描工具上的工作站，用于同时输入食谱和对扫描工具和扫描工具配方数据库的配方更改。

公开(公告)号：US06377898B1

公开(公告)日：2002-04-23

申请号：US09294246

申请日：1999-04-19

申请人： Paul J. Steffan ,  Allen S. Yu

发明人： Paul J. Steffan ,  Allen S. Yu

IPC分类号： G06F1900

CPC分类号： H01L22/20

摘要： A method of analyzing and classifying defects on semiconductor wafers during a semiconductor manufacturing process using a comparator die selector system wherein an automatic defect classification review tool compares defects on a die location with an identical location on an identical die. The automatic defect classification review tool locates identical die with information from the comparator die selector system.

摘要翻译： 一种在使用比较模片选择系统的半导体制造过程中对半导体晶片上的缺陷进行分析和分类的方法，其中自动缺陷分类评估工具将模具位置上的缺陷与相同模具上的相同位置进行比较。 自动缺陷分类检查工具与来自比较器管芯选择器系统的信息定位相同的管芯。

公开(公告)号：US06291252B1

公开(公告)日：2001-09-18

申请号：US09345175

申请日：1999-06-30

申请人： Allen S. Yu ,  Paul J. Steffan

发明人： Allen S. Yu ,  Paul J. Steffan

IPC分类号： H01L2100

CPC分类号： H01L21/67276 ,  Y10T29/41

摘要： A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafer is automatically processed. If the tool has been on idle beyond the predetermined period of time, a conditioning wafer is automatically processed.

摘要翻译： 一种在处理工具中制造半导体晶片的方法，其中确定工具是否已经在预定时间段之后空转。 如果工具在预定时间之后没有闲置，则产品晶片被自动处理。 如果工具在预定时间段之后已经空转，则调节晶片被自动处理。

公开(公告)号：US06274443B1

公开(公告)日：2001-08-14

申请号：US09162116

申请日：1998-09-28

申请人： Allen S. Yu ,  Patrick K. Cheung ,  Paul J. Steffan

发明人： Allen S. Yu ,  Patrick K. Cheung ,  Paul J. Steffan

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

摘要翻译： 通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以使所得到的LDD结构远离所述第二多晶硅的边缘 随后将形成具有基本垂直轮廓的多晶硅栅极。 由于LDD结构与第二多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减小。