公开(公告)号：US20090294861A1

公开(公告)日：2009-12-03

申请号：US12466733

申请日：2009-05-15

申请人： Olivier THOMAS ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

发明人： Olivier THOMAS ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises:a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line,a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level,the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.

摘要翻译： 一种非易失性随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平处，其中至少一个第一存取晶体管和至少一个第二存取晶体管 ，其分别布置在第一位线和第一存储节点之间，以及第二位线和第二存储节点之间，第一存取晶体管和第二存取晶体管具有连接到字线的栅极，第二多个 形成触发器并且位于所述堆叠的至少另一个层级下面的所述给定电平以下的所述第二多个晶体管的晶体管分别包括与所述第一多个晶体管的沟道区相对的栅电极 的晶体管，并且通过提供用于使得所述栅极电极和所述沟道区域耦合的绝缘区域与该沟道区域分离。

公开(公告)号：US20090289304A1

公开(公告)日：2009-11-26

申请号：US12296402

申请日：2007-03-30

申请人： Arnaud Pouydebasque ,  Robin Cerutti

发明人： Arnaud Pouydebasque ,  Robin Cerutti

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/785

摘要： The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET-channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs.

摘要翻译： 本发明涉及具有取向硅表面的SOI衬底上的CMOS电路器件，在第一衬底区域上包括具有第一导电类型的FET沟道区的FET，并且在第二衬底区域上包括具有 与第一导电类型相反的第二导电类型的FinFET沟道区。 本发明还涉及制造这种CMOS电路器件的方法。 多栅平面FET的制造包括在中间步骤中，形成具有FET材料和牺牲材料的层的交替序列并且包含主FET沟道面的FET沟道堆叠，其具有与 定向硅表面。 根据本发明，实现了多栅极FET器件的共同集成，确保了NMOS和PMOS FET的高载流子迁移率。