公开(公告)号：US12112975B2

公开(公告)日：2024-10-08

申请号：US18346622

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Yan-Ting Lin ,  Clement Hsingjen Wann

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02321 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/31155 ,  H01L21/76237 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/02296 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66803

Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

公开(公告)号：US20240332188A1

公开(公告)日：2024-10-03

申请号：US18742102

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Gerben DOORNBOS

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/481 ,  H01L27/0924 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate.

公开(公告)号：US12107135B2

公开(公告)日：2024-10-01

申请号：US17467660

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US20240313116A1

公开(公告)日：2024-09-19

申请号：US18670123

申请日：2024-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2029/7858

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US12046675B2

公开(公告)日：2024-07-23

申请号：US18234043

申请日：2023-08-15

Applicant: Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Dinesh Maheshwari ,  Yuniarto Widjaja

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  G06F11/10 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52

CPC classification number: H01L29/7841 ,  H01L27/1211 ,  H10B12/20 ,  G06F11/1068 ,  G11C7/02 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52 ,  H01L29/785

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

公开(公告)号：US12027608B2

公开(公告)日：2024-07-02

申请号：US17325622

申请日：2021-05-20

Applicant: DO NOT USE—Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Ming-Ching Chang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

公开(公告)号：US20240215267A1

公开(公告)日：2024-06-27

申请号：US18596623

申请日：2024-03-06

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

Abstract: A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

公开(公告)号：US20240186418A1

公开(公告)日：2024-06-06

申请号：US18552811

申请日：2022-03-18

Applicant: Brandenburgische Technische Universität Cottbus-Senftenberg, Körperschaft des Öffentlichen Rechts

Inventor： Ulrich WULF ,  Hans RICHTER

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/08

CPC classification number: H01L29/7855 ,  H01L27/1211 ,  H01L29/0847

Abstract: The disclosure relates to a double-gate four-terminal semiconductor component comprising a substrate, an electrically insulating cover layer on the substrate, a fin-type channel region situated above the substrate and composed of a doped semiconductor material of a first conductivity type having two mutually opposite longitudinal sides extending along a longitudinal direction of the channel region, the channel region having a first end and a second end in the longitudinal direction, a first and a second gate electrode, which are situated on the cover layer and are arranged opposite one another each on one of the longitudinal sides of the channel region and are each electrically insulated from the longitudinal sides by an insulation layer, a first and a second contact region situated on the cover layer and composed of a semiconductor material of a second conductivity type.

公开(公告)号：USRE49988E1

公开(公告)日：2024-05-28

申请号：US17569902

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/775 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US20240170340A1

公开(公告)日：2024-05-23

申请号：US18425390

申请日：2024-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.