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11.发明申请公开(公告)号：US20110116311A1
公开(公告)日：2011-05-19
申请号：US12778524
申请日：2010-05-12
申请人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
发明人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
CPC分类号： G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
摘要翻译： 在所公开的一个或多个实施例中，可以通过在编程电压下偏置所选择的字线来对存储器件中的穿通干扰效应进行减小，以对所选择的存储单元进行编程，从而对串联串的漏极侧的字线进行偏置 利用Vpass电压，将相邻的存储单元关闭到所选择的存储单元，并且以小于Vpass的Vlow电压偏置关断存储单元的源极侧的剩余字线。
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公开(公告)号：US20080056008A1
公开(公告)日：2008-03-06
申请号：US11513891
申请日：2006-08-31
申请人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
发明人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。
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13.发明授权公开(公告)号：US07733705B2
公开(公告)日：2010-06-08
申请号：US12047841
申请日：2008-03-13
申请人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
发明人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
摘要翻译： 可以通过在编程电压下偏置所选择的字线来对所选存储单元进行编程来减少存储器件中的穿通干扰效应，以Vpass电压偏置串联串的漏极侧的字线，关闭相邻的 存储单元，并且以小于Vpass的Vlow电压偏置关断存储单元的源极侧的剩余字线。
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公开(公告)号：US08891309B2
公开(公告)日：2014-11-18
申请号：US13272336
申请日：2011-10-13
申请人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
发明人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。
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公开(公告)号：US08405444B2
公开(公告)日：2013-03-26
申请号：US13542250
申请日：2012-07-05
IPC分类号： H03K17/687
CPC分类号： G11C7/12 , H03K3/35613 , H03K19/018528
摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
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公开(公告)号：US08217705B2
公开(公告)日：2012-07-10
申请号：US12775131
申请日：2010-05-06
IPC分类号： H03K17/687
CPC分类号： G11C7/12 , H03K3/35613 , H03K19/018528
摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
摘要翻译： 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。
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公开(公告)号：US07684243B2
公开(公告)日：2010-03-23
申请号：US11513891
申请日：2006-08-31
申请人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
发明人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。
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公开(公告)号：US20120269011A1
公开(公告)日：2012-10-25
申请号：US13542250
申请日：2012-07-05
CPC分类号： G11C7/12 , H03K3/35613 , H03K19/018528
摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
摘要翻译： 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。
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19.发明授权公开(公告)号：US08164950B2
公开(公告)日：2012-04-24
申请号：US12778524
申请日：2010-05-12
申请人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
发明人： Alessandro Torsi , Carlo Musilli , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
摘要翻译： 可以通过在编程电压下偏置所选择的字线来对所选存储单元进行编程来减少存储器件中的穿通干扰效应，以Vpass电压偏置串联串的漏极侧的字线，关闭相邻的 存储单元，并且以小于Vpass的Vlow电压偏置关断存储单元的源极侧的剩余字线。
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公开(公告)号：US08059474B2
公开(公告)日：2011-11-15
申请号：US12706357
申请日：2010-02-16
申请人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
发明人： Seiichi Aritome , Alessandro Torsi , Carlo Musilli
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。
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