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    REDUCTION OF PUNCH-THROUGH DISTURB DURING PROGRAMMING OF A MEMORY DEVICE
    2.
    发明申请
    REDUCTION OF PUNCH-THROUGH DISTURB DURING PROGRAMMING OF A MEMORY DEVICE 有权
    在存储器件编程期间减少冲击干扰

    公开(公告)号：US20110116311A1

    公开(公告)日：2011-05-19

    申请号：US12778524

    申请日：2010-05-12

    Applicant: Alessandro Torsi ,  Carlo Musilli ,  Seiichi Aritome

    Inventor： Alessandro Torsi ,  Carlo Musilli ,  Seiichi Aritome

    IPC: G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

    Abstract: In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.

    Abstract translation: 在所公开的一个或多个实施例中，可以通过在编程电压下偏置所选择的字线来对存储器件中的穿通干扰效应进行减小，以对所选择的存储单元进行编程，从而对串联串的漏极侧的字线进行偏置 利用Vpass电压，将相邻的存储单元关闭到所选择的存储单元，并且以小于Vpass的Vlow电压偏置关断存储单元的源极侧的剩余字线。

    REDUCING READ FAILURE IN A MEMORY DEVICE
    5.
    发明申请
    REDUCING READ FAILURE IN A MEMORY DEVICE 有权
    减少存储设备中的读取故障

    公开(公告)号：US20120051139A1

    公开(公告)日：2012-03-01

    申请号：US13272336

    申请日：2011-10-13

    Applicant: Seiichi ARITOME ,  Alessandro TORSI ,  Carlo MUSILLI

    Inventor： Seiichi ARITOME ,  Alessandro TORSI ,  Carlo MUSILLI

    IPC: G11C16/06 ,  G11C16/04

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

    Abstract translation: 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

    REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
    6.
    发明申请
    REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE 有权
    减少存储器件中擦除干扰的影响

    公开(公告)号：US20110128782A1

    公开(公告)日：2011-06-02

    申请号：US12628522

    申请日：2009-12-01

    Applicant: Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    Inventor： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    IPC: G11C7/00 ,  G11C16/10

    CPC classification number: G11C16/3418 ,  G11C16/0483 ,  G11C16/14

    Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

    Abstract translation: 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

    Reducing read failure in a memory device
    7.
    发明申请
    Reducing read failure in a memory device 有权
    减少存储设备中的读取失败

    公开(公告)号：US20080056008A1

    公开(公告)日：2008-03-06

    申请号：US11513891

    申请日：2006-08-31

    Applicant: Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

    Inventor： Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

    IPC: G11C16/04

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

    Abstract translation: 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

    Reducing read failure in a memory device
    8.
    发明授权
    Reducing read failure in a memory device 有权
    减少存储设备中的读取失败

    公开(公告)号：US08891309B2

    公开(公告)日：2014-11-18

    申请号：US13272336

    申请日：2011-10-13

    Applicant: Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

    Inventor： Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

    Abstract translation: 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

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