公开(公告)号：US20140225223A1

公开(公告)日：2014-08-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与传统技术相比，制造金属 - 绝缘体 - 金属（MIM）电容器的方法减少了掩模和处理步骤的数量。 在半导体芯片上构图导电再分布层（RDL）。 MIM电介质层沉积在RDL上。 在MIM电介质层上沉积MIM电容器的第一导电层。 使用MIM导电层掩模对MIM电介质层进行构图。 导电再分配层包括在MIM电容器的第一导电层下延伸的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140211546A1

公开(公告)日：2014-07-31

申请号：US13869110

申请日：2013-04-24

Applicant: Industry-Academic Cooperation Foundation, Yonsei University ,  QUALCOMM INCORPORATED

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。