公开(公告)号：US10247617B2

公开(公告)日：2019-04-02

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  G01K7/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  G01K7/18 ,  H01L23/34 ,  H01L23/522 ,  H01L27/06

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US20140225223A1

公开(公告)日：2014-08-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与传统技术相比，制造金属 - 绝缘体 - 金属（MIM）电容器的方法减少了掩模和处理步骤的数量。 在半导体芯片上构图导电再分布层（RDL）。 MIM电介质层沉积在RDL上。 在MIM电介质层上沉积MIM电容器的第一导电层。 使用MIM导电层掩模对MIM电介质层进行构图。 导电再分配层包括在MIM电容器的第一导电层下延伸的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140197520A1

公开(公告)日：2014-07-17

申请号：US13743434

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  Bin Yang ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L28/24

Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.

Abstract translation: 在特定实施例中，一种方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露光学平坦化层的区域。 至少部分地在该区域内形成电阻层。 该方法还包括去除光学平坦化层的至少第二部分和电阻层的至少第三部分以形成电阻器。

公开(公告)号：US20250118645A1

公开(公告)日：2025-04-10

申请号：US18987457

申请日：2024-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H10D1/68

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US20230223341A1

公开(公告)日：2023-07-13

申请号：US17573461

申请日：2022-01-11

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong Zhu ,  Giridhar Nallapati

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/53266 ,  H01L23/5283 ,  H01L23/53223 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76831

Abstract: An interconnect structure comprising a low via resistance via structure is disclosed. The via structure comprises a barrier layer on sidewalls and at bottom of the via structure. The interconnect structure also includes a first metal layer. The interconnect structure further includes a second metal layer between the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials.

公开(公告)号：US20180204765A1

公开(公告)日：2018-07-19

申请号：US15408796

申请日：2017-01-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L21/033

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/3086 ,  H01L27/0207 ,  H01L27/11807

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

公开(公告)号：US09818817B2

公开(公告)日：2017-11-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

公开(公告)号：US09070551B2

公开(公告)日：2015-06-30

申请号：US13974135

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Benjamin John Bowers ,  James W. Hayward ,  Charanya Gopal ,  Gregory Christopher Burda ,  Robert J. Bucki ,  Chock H. Gan ,  Giridhar Nallapati ,  Matthew D. Youngblood ,  William R. Flederbach

IPC: G06F17/50 ,  H01L27/02 ,  H01L21/22 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/22 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/66825 ,  Y02P90/265

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract translation: 用于设计集成电路的单元库，该库包括连续扩散兼容（CDC）单元。 CDC单元包括电连接到电源轨的p掺杂扩散区，并且连接于CDC单元的左边缘到右边缘; 第一多晶硅栅极，设置在p掺杂扩散区上方并电连接到p掺杂扩散区; 电连接到接地导轨并从左边缘到右边缘连续的n掺杂扩散区域; 第二多晶硅栅极，其设置在所述n掺杂扩散区域上方并电连接到所述n掺杂扩散区域; 设置在p掺杂和n掺杂扩散区上并靠近左边缘的左浮动多晶硅栅极; 以及设置在p掺杂和n掺杂扩散区域上并且靠近右边缘的右浮动多晶硅栅极。

公开(公告)号：US20140264629A1

公开(公告)日：2014-09-18

申请号：US13829864

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Giridhar Nallapati ,  Chidi Chidambaram

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.

Abstract translation: 提供局部互连结构，其包括通过扩散导向的局部互连耦合到相邻栅极层的栅极定向局部互连。

公开(公告)号：US08836040B2

公开(公告)日：2014-09-16

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。