公开(公告)号：US20160077973A1

公开(公告)日：2016-03-17

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。

公开(公告)号：US20240370376A1

公开(公告)日：2024-11-07

申请号：US18522049

申请日：2023-11-28

Applicant: QUALCOMM Incorporated

Inventor： Subbarao PALACHARLA ,  Hiral NANDU ,  George PATSILARAS ,  Simon Peter William BOOTH ,  Rakesh Kumar GUPTA ,  Kedar BHOLE

IPC: G06F12/0888

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

公开(公告)号：US20230214330A1

公开(公告)日：2023-07-06

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral NANDU ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Alain ARTIERI ,  Simon Peter William BOOTH ,  Vipul GANDHI ,  Girish BHAT ,  Yen-Kuan WU ,  Younghoon KIM

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US20220113901A1

公开(公告)日：2022-04-14

申请号：US17068293

申请日：2020-10-12

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund TURNER ,  George PATSILARAS ,  Zhenbiao MA ,  Subbarao PALACHARLA ,  Bohuslav RYCHLIK ,  Tarek ZGHAL ,  Christopher KOOB

IPC: G06F3/06

Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.

公开(公告)号：US20200004687A1

公开(公告)日：2020-01-02

申请号：US16565882

申请日：2019-09-10

Applicant: QUALCOMM Incorporated

Inventor： Farrukh HIJAZ ,  George PATSILARAS

IPC: G06F12/0897 ,  G06F12/0877 ,  G06F12/0891

Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.