公开(公告)号：US20190056990A1

公开(公告)日：2019-02-21

申请号：US15682533

申请日：2017-08-21

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/10

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

公开(公告)号：US20220350749A1

公开(公告)日：2022-11-03

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Rakesh Kumar GUPTA ,  Subbarao PALACHARLA ,  Kedar BHOLE ,  Laurent Rene MOLL ,  Carlo SPITALE ,  Sparsh SINGHAI ,  Shyamkumar THOZIYOOR ,  Gopi TUMMALA ,  Christophe AVOINNE ,  Samir GINDE ,  Syed Minhaj HASSAN ,  Jean-Jacques LECLER ,  Luigi VINCI

IPC: G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

公开(公告)号：US20230214330A1

公开(公告)日：2023-07-06

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral NANDU ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Alain ARTIERI ,  Simon Peter William BOOTH ,  Vipul GANDHI ,  Girish BHAT ,  Yen-Kuan WU ,  Younghoon KIM

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US20180314586A1

公开(公告)日：2018-11-01

申请号：US15942372

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Alain ARTIERI ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Dexter Tamio CHUN ,  Jungwon SUH

IPC: G06F11/10 ,  G06F3/06

CPC classification number: H04L1/0041 ,  H03M13/19 ,  H04L1/0045 ,  H04L1/0057

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

公开(公告)号：US20210133100A1

公开(公告)日：2021-05-06

申请号：US16823306

申请日：2020-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Jean-Jacques LECLER ,  Shyamkumar THOZIYOOR

IPC: G06F12/06 ,  G06F12/1018 ,  G06F12/0864 ,  G06F12/02

Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.

公开(公告)号：US20190324850A1

公开(公告)日：2019-10-24

申请号：US16503368

申请日：2019-07-03

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

IPC: G06F11/10 ,  G06F3/06

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.