公开(公告)号：US09195466B2

公开(公告)日：2015-11-24

申请号：US13676146

申请日：2012-11-14

Applicant: QUALCOMM Incorporated

Inventor： Melinda J. Brown ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Andrew S. Irwin ,  Michael William Morrow

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。 在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。 该电路还基于评估与第一条件逻辑相反的第二条件，检测向目标寄存器写入第二值的第二条件写入指令。 选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。 如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

公开(公告)号：US20160291981A1

公开(公告)日：2016-10-06

申请号：US14679408

申请日：2015-04-06

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Michael William Morrow ,  Derek Jay Conrod ,  Bohuslav Rychlik

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3832

Abstract: Removing invalid literal load values, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load table containing one or more entries comprising an address and a cached literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit removes the literal load instruction from the instruction stream, and provides the cached literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit further determines whether an invalidity indicator for the literal load table has been received. If so, the instruction processing circuit flushes the literal load table. The invalidity indicator may be generated responsive to modification of a constant table.

Abstract translation: 公开了删除无效文字负载值以及相关电路，方法和计算机可读介质。 在一个方面，指令处理电路提供包含一个或多个条目的文字加载表，该条目包括地址和缓存的字面负载值。 在指令流中检测到文字加载指令时，指令处理电路确定文字加载表是否包含具有文字加载指令地址的条目。 如果是这样，则指令处理电路从指令流中去除文字加载指令，并将存储在该条目中的缓存的文字加载值提供给至少一个从属指令。 指令处理电路还确定是否已经接收到文字负载表的无效指示符。 如果是这样，指令处理电路刷新文字负载表。 可以响应于常数表的修改来生成无效指示符。

公开(公告)号：US20160092219A1

公开(公告)日：2016-03-31

申请号：US14499764

申请日：2014-09-29

Applicant: QUALCOMM Incorporated

Inventor： Michael William Morrow

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/30167 ,  G06F9/34 ,  G06F9/3832

Abstract: Accelerating constant value generation using a computed constants table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a computed constants table containing one or more entries each comprising an address and a constant value. The instruction processing circuit is configured to detect, in an instruction stream, a constant-generating instruction sequence, and to determine whether an address of the constant-generating instruction sequence is present in an entry of the computed constants table. If the address of the constant-generating instruction sequence is present in the entry of the computed constants table, the instruction processing circuit provides a constant value stored in the entry for execution of at least one dependent instruction on the constant-generating instruction sequence. In this manner, the generation of constant values by a constant-generating instruction sequence may be accelerated, allowing dependent instructions to use the constant values with zero-cycle latency.

Abstract translation: 公开了使用计算常数表加速恒定值生成，以及相关电路，方法和计算机可读介质。 在一个方面，指令处理电路提供包含一个或多个条目的计算常数表，每个条目包括地址和常数值。 指令处理电路被配置为在指令流中检测恒定生成指令序列，并且确定常数生成指令序列的地址是否存在于计算出的常数表的条目中。 如果常数生成指令序列的地址存在于计算出的常数表的条目中，则指令处理电路提供存储在该条目中的恒定值，以执行关于恒定生成指令序列的至少一个相关指令。 以这种方式，可以加速通过恒定生成指令序列产生恒定值，从而允许相关指令使用零周期等待时间的常数值。

公开(公告)号：US20160077836A1

公开(公告)日：2016-03-17

申请号：US14484659

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Michael William Morrow

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/30043 ,  G06F9/30167 ,  G06F9/3832

Abstract: Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load prediction table containing one or more entries, each comprising an address and a literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load prediction table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit provides the predicted literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit subsequently determines whether the predicted literal load value matches the actual literal load value loaded by the literal load instruction. If a mismatch exists, the instruction processing circuit initiates a misprediction recovery. The at least one dependent instruction is re-executed using the actual literal load value.

Abstract translation: 公开了使用文字负载预测表以及相关电路，方法和计算机可读介质来预测文字负载值。 在一个方面，指令处理电路提供包含一个或多个条目的文字负载预测表，每个条目包括地址和文字负载值。 在指令流中检测到文字加载指令时，指令处理电路确定文字负载预测表是否包含具有文字加载指令的地址的条目。 如果是这样，则指令处理电路将存储在条目中的预测文字负载值提供给至少一个依赖指令。 指令处理电路随后确定预测的文字负载值是否与文字加载指令加载的实际文字负载值相匹配。 如果存在不匹配，则指令处理电路启动错误预测恢复。 使用实际文字负载值重新执行至少一个依赖指令。

公开(公告)号：US09146741B2

公开(公告)日：2015-09-29

申请号：US13655622

申请日：2012-10-19

Applicant: QUALCOMM Incorporated

Inventor： Melinda J. Brown ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Brian Michael Stempel ,  Michael Scott McIlvaine

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30018 ,  G06F9/3838

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. In this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中消除冗余掩蔽操作。 在一个实施例中，由指令处理电路检测指示将值写入第一寄存器的操作的指令流中的第一指令，该值具有小于第一寄存器的大小的值。 电路还检测指示流中指示在第一寄存器上的屏蔽操作的第二指令。 在确定掩蔽操作指示对第一寄存器的读取操作和写入操作并且具有等于或大于值大小的身份掩码大小的情况下，屏蔽操作被消除。 以这种方式，消除掩蔽操作可避免潜在的写后危害，并通过从执行流水线中删除冗余操作来提高CPU性能。

公开(公告)号：US20140149726A1

公开(公告)日：2014-05-29

申请号：US13792335

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： James Norris Dieffenderfer ,  Michael William Morrow ,  Michael Scott McIlvaine ,  Daren Eugene Streett ,  Vimal K. Reddy ,  Brian Michael Stempel

IPC: G06F9/38

CPC classification number: G06F9/3808 ,  G06F9/30054

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract translation: 建立用于子程序的分支目标指令缓存（BTIC）条目返回以减少管道气泡，以及相关系统，方法和计算机可读介质。 在一个实施例中，建立BTIC条目的方法包括检测执行流水线中的子程序调用。 作为响应，在子程序返回的BTIC条目中写入与子程序调用顺序取得的至少一个指令作为分支目标指令。 计算下一个指令提取地址，并将其写入BTIC条目中的下一个指令获取地址字段。 以这种方式，即使第一次遇到子程序返回或从不同的呼叫位置调用子程序，BTIC可以为子程序返回提供正确的分支目标指令和下一个指令获取地址数据。

公开(公告)号：US20140149722A1

公开(公告)日：2014-05-29

申请号：US13686229

申请日：2012-11-27

Applicant: QUALCOMM INCORPORATED

Inventor： Melinda J. Brown ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Brian Michael Stempel ,  Michael Scott McIlvaine ,  Rodney Wayne Smith ,  Jeffrey M. Schottmiller ,  Andrew S. Irwin

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30167

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register. In this manner, conversion of multiple instructions for generating a constant into the fused instruction(s) removes the potential for a read-after-write hazard and associated consequences caused by dependencies between certain instructions, while reducing a number of clock cycles required to process the instructions.

Abstract translation: 公开了立即值的融合，指令处理电路中的基于写入的指令以及相关的处理器系统，方法和计算机可读介质。 在一个实施例中，指令处理电路检测指示向寄存器写入立即值的操作的第一指令。 电路还检测至少一个后续指令，指示在保持寄存器的第二部分的值的同时重写寄存器的至少一个第一部分的操作。 所述至少一个后续指令被转换（或替代）与一个融合指令，其指示写入寄存器的至少一个第一部分和第二部分的操作。 以这种方式，将用于产生常数的多个指令转换为融合指令消除了读写后危险和由特定指令之间的依赖性引起的相关后果的可能性，同时减少了处理所需的时钟周期数 说明。