公开(公告)号：US20140281440A1

公开(公告)日：2014-09-18

申请号：US13842835

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Jiajin Tu ,  Suresh K. Venkumahanti ,  Brian R. Mestan

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3846 ,  G06F9/3861

Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Abstract translation: 将部分目标地址存储在指令高速缓存中的示例性方法包括接收分支指令。 该方法还包括预测不采用分支指令的方向。 该方法还包括基于执行分支指令来计算目的地地址。 该方法还包括使用目的地址确定部分目标地址。 该方法进一步包括响应于从未被采取的分支指令的预测方向改变，替换部分目标地址的指令高速缓存中的偏移。

公开(公告)号：US20140244986A1

公开(公告)日：2014-08-28

申请号：US13776947

申请日：2013-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Prasanna Kumar Balasundaram ,  Suresh K. Venkumahanti

IPC: G06F9/30

CPC classification number: G06F11/3656 ,  G06F11/3636

Abstract: A system and method to select a packet format based on a number of executed threads is disclosed. In a particular embodiment, a method includes determining, at a multi-threaded processor, a number of threads of a plurality of threads executing during a time period. A packet format is determined from a plurality of formats based at least in part on the determined number of threads. Data associated with execution of an instruction by a particular thread is stored in accordance with the selected format in a memory (e.g., a buffer).

Abstract translation: 公开了一种基于执行线程数来选择分组格式的系统和方法。 在特定实施例中，一种方法包括在多线程处理器处确定在一段时间段内执行的多个线程的线程数。 至少部分地基于确定的线程数从多种格式确定分组格式。 与特定线程执行指令相关联的数据根据​​选择的格式存储在存储器（例如，缓冲器）中。

公开(公告)号：US20140201494A1

公开(公告)日：2014-07-17

申请号：US13741981

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Suresh K. Venkumahanti ,  Erich J. Plondke ,  Lucian Codrescu ,  Shane M. Mahon ,  Rahul R. Toley ,  Fadi A. Hamdan

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.

Abstract translation: 一种装置包括翻译后备缓冲器（TLB）。 TLB包括至少一个条目，其包括条目虚拟地址和对应于条目页面的条目页面大小指示。 该装置还包括被配置为接收输入页面大小指示和与输入页面相对应的输入虚拟地址的输入逻辑。 该装置还包括重叠检查逻辑，其被配置为至少部分地基于条目页面大小指示和输入页面大小指示来确定输入页面是否与入口页面重叠。

公开(公告)号：US20140201449A1

公开(公告)日：2014-07-17

申请号：US13741917

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F9/3455 ,  G06F9/3832 ,  G06F2212/6082

Abstract: In a particular embodiment, a method, includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based, on the instruction will access the way.

Abstract translation: 在特定实施例中，一种方法包括识别指令的一种或多种方式预测特性。 该方法还包括基于一个或多个方式预测特征的识别来选择性地读取用于标识与标识数据高速缓存的方式相关联的表的条目的表。 该方法还包括基于指令访问数据高速缓存的下一次访问来进行预测。