公开(公告)号：US20240321369A1

公开(公告)日：2024-09-26

申请号：US18186734

申请日：2023-03-20

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H10B20/25

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L23/5256 ,  H10B20/25

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a conductive element on an isolation structure, a dielectric film, a first contact structure, wherein at least a portion of the dielectric film is disposed between the conductive element and the first contact structure, and a second contact structure disposed on and electrically coupled with the conductive element. The dielectric film is configured as a resistive element with the first contact structure and the second contact structure being terminals of the resistive element after a dielectric breakdown has occurred within the portion of the dielectric film. Also, the dielectric film is configured as an insulator of a capacitive element with the first contact structure and the second contact structure being terminals of the capacitive element in a case that no dielectric breakdown has occurred within the portion of the dielectric film.

公开(公告)号：US20240319127A1

公开(公告)日：2024-09-26

申请号：US18189494

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: G01N27/22

CPC classification number: G01N27/225 ,  G01N27/228

Abstract: In an aspect, a device includes: a first patterned metal layer; a first dielectric layer disposed over the first patterned metal layer; a second patterned metal layer disposed over the first dielectric layer, wherein the first patterned metal layer, the first dielectric layer, and the second patterned metal layer form a first capacitor; a second moisture-sensitive dielectric layer disposed over the second patterned metal layer; and a third patterned metal layer disposed over the second moisture-sensitive dielectric layer, wherein the third patterned metal layer, the second moisture-sensitive dielectric layer, and the second patterned metal layer form a second capacitor that is moisture-sensitive, and the first patterned metal layer is further configured as a heating element to assist in removing moisture from the second moisture-sensitive dielectric layer of the second capacitor in response to provision of an electrical power to the first patterned metal layer.

公开(公告)号：US20230352583A1

公开(公告)日：2023-11-02

申请号：US17661221

申请日：2022-04-28

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Ravi Pramod Kumar VEDULA ,  Hyunchul JUNG

IPC: H01L29/78 ,  H01L29/66 ,  H03F3/21

CPC classification number: H01L29/7835 ,  H01L29/66492 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/451

Abstract: Disclosed is a transistor of a device that has an asymmetric resistance or an asymmetric capacitive coupling or both. When used in a cascode configuration in an amplifier, low current performance of the amplifier is improved. Asymmetric resistance may be enabled through differentially doping source and drain structures of the transistor and/or through differentially manipulating geometries the source and drain structures. Asymmetric capacitive coupling may be enabled through providing dielectrics and differentially locating the dielectrics above a gate of the transistor. Further, a body of the transistor may be biased.

公开(公告)号：US20220093740A1

公开(公告)日：2022-03-24

申请号：US17410513

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed are apparatuses and related methods for fabrication. The apparatus includes a field-effect transistor (FET). The FET has a source contact coupled to a source implant in a body layer, a drain contact coupled to a drain implant in the body layer, and a first gate coupled to a transistor channel in the body layer between the source contact and the drain contact. The FET further includes a second gate coupled to the body layer between the source contact and the drain contact, a drift region in the body layer, where the second gate at least partially overlaps the drift region, and a resurf portion disposed partially over the first gate and over the second gate.