公开(公告)号：US20240349496A1

公开(公告)日：2024-10-17

申请号：US18044141

申请日：2022-03-22

Applicant: CHENGDU PBM TECHNOLOGY LTD.

Inventor： KE WANG ,  JACK ZEZHONG PENG

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A three-dimensional multilayer memory with interconnection of low-resistance silicides and a manufacturing method thereof are provided. The three-dimensional multilayer memory comprises an underlying circuit part and a base structure disposed on the underlying circuit part. The base structure is divided into two interdigitated structures which are independent of each other by a curved division trench, and comprises first conductive medium layers and insulating medium layers which are alternately stacked on each other. At least three memory cell holes are disposed side by side in the curved division trench, wherein a vertical electrode is disposed in each memory cell hole, and an insulating isolation pillar is disposed between two adjacent memory cell holes. The first conductive medium layers each comprise a low-resistance semiconductor layer and a low-resistance silicide layer, one stacking on top of the other. An insulating region is disposed in the low-resistance silicide layer, close to a storage medium.

公开(公告)号：US20240324191A1

公开(公告)日：2024-09-26

申请号：US18413085

申请日：2024-01-16

Applicant: eMemory Technology Inc.

Inventor： Lun-Chun CHEN ,  Ping-Lung HO

IPC: H10B20/25 ,  G11C17/16 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H10B20/25 ,  G11C17/165 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

公开(公告)号：US20240292610A1

公开(公告)日：2024-08-29

申请号：US18586440

申请日：2024-02-24

Applicant: STMicroelectronics International N.V.

Inventor： Pascal FORNARA

IPC: H10B20/25 ,  G11C17/06 ,  G11C17/18 ,  H10B99/00

CPC classification number: H10B20/25 ,  G11C17/06 ,  G11C17/18 ,  H10B99/16

Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.

公开(公告)号：US20240268107A1

公开(公告)日：2024-08-08

申请号：US18165296

申请日：2023-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Shao-Tung PENG ,  Chung-I HUANG

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: An integrated circuit includes a first active region, a second active region, a first fuse and a dummy fuse. The first active region extends in a first direction, and is on a first level. The second active region extends in the first direction, is on the first level, and is separated from the first active region in a second direction different from the first direction. The first fuse extends in the first direction, is on a second level, overlaps the first active region and is electrically coupled to the first active region. The dummy fuse extends in the first direction, is on the second level, and is separated from the first fuse in the second direction. The dummy fuse overlaps the second active region, and is not electrically coupled to the second active region.

公开(公告)号：US20230354593A1

公开(公告)日：2023-11-02

申请号：US18345558

申请日：2023-06-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keiichi HONDA

IPC: H10B20/25 ,  H01L23/528 ,  H01L23/66

CPC classification number: H10B20/25 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6605

Abstract: A semiconductor substrate includes a fuse memory that is a write-once memory, a control unit that writes and reads data to and from the fuse memory, and a digital. A wiring layer includes a wiring conductor that connects the digital and an external connection terminal and a plane conductor provided in between the wiring conductor and a surface of the semiconductor substrate. The wiring conductor overlaps the fuse memory when the wiring conductor and the fuse memory are seen in a stacking direction in which the semiconductor substrate and the wiring layer are stacked on top of each other. The plane conductor is arranged in between the wiring conductor and the fuse memory and is connected to a ground potential

公开(公告)号：US20230247827A1

公开(公告)日：2023-08-03

申请号：US18134041

申请日：2023-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

公开(公告)号：US20240347374A1

公开(公告)日：2024-10-17

申请号：US18135339

申请日：2023-04-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-CHUNG HSU ,  EN-JUI LI

IPC: H01L21/762 ,  H10B10/00 ,  H10B12/00 ,  H10B20/25

CPC classification number: H01L21/76224 ,  H10B10/18 ,  H10B12/30 ,  H10B20/25

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

公开(公告)号：US20240297115A1

公开(公告)日：2024-09-05

申请号：US18333189

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Meng-Sheng Chang ,  Chung-Sheng Yuan ,  Yi-Kan Cheng

IPC: H01L23/525 ,  G11C17/16 ,  H01L23/522 ,  H01L23/528 ,  H10B20/25

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L23/5226 ,  H01L23/5283 ,  H10B20/25 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite the first surface. The semiconductor structure includes a semiconductor device disposed on the first surface. The semiconductor structure includes a metallization layer disposed on the second surface. The semiconductor structure includes a first conductive via and a second conductive via coupled in parallel to the metallization layer, the first conductive via and the second conductive via extending from the second side toward the first side. The semiconductor structure further includes an electrical fuse disposed over the semiconductor device and coupled to the first and second conductive vias.

公开(公告)号：US20240179896A1

公开(公告)日：2024-05-30

申请号：US18089063

申请日：2022-12-27

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H10B20/25 ,  G11C17/18

CPC classification number: H10B20/25 ,  G11C17/18

Abstract: A 1.5T one-time programmable memory device and a method for fabricating it re disclosed. The 1.5T OTP memory device includes at least one 1.5T memory cell formed in an active area of a semiconductor substrate. The 1.5T memory cell includes one select transistor and one half of a grounding transistor. This structure is simple. Moreover, in the grounding transistor, a portion of a thin gate dielectric layer is sandwiched between a doped junction region coupled to a source region in the select transistor and a grounding gate. During programming of the 1.5T memory cell, a voltage on the drain region in the select transistor can be coupled to the doped junction region to cause the thin gate dielectric layer portion sandwiched between the doped junction region and the grounding gate to rupture at a low programming voltage.

公开(公告)号：US20240087660A1

公开(公告)日：2024-03-14

申请号：US17953717

申请日：2022-09-27

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: G11C17/12 ,  H10B20/25

CPC classification number: G11C17/12 ,  H10B20/25

Abstract: The present invention relates to an OTP memory device, a method for operating the OTP memory device and a method for fabricating the OTP memory device. In the OTP memory device, a PN junction is formed between a source-side LDD region and a source region in each OTP memory cell. During programming of the OTP memory cell, the PN junction is broken down, providing one-time programmability. Moreover, its circuit layout is simple, helping to achieve a reduced chip area and lower cost. In the method for fabricating the OTP memory device, OTP memory cells in the OTP memory device and MOS transistors are simultaneously formed on surface regions of a semiconductor substrate, reducing fabrication complexity and cost of the OTP memory device and making it suitable for mass production.