公开(公告)号：US20160291981A1

公开(公告)日：2016-10-06

申请号：US14679408

申请日：2015-04-06

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Michael William Morrow ,  Derek Jay Conrod ,  Bohuslav Rychlik

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3832

Abstract: Removing invalid literal load values, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load table containing one or more entries comprising an address and a cached literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit removes the literal load instruction from the instruction stream, and provides the cached literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit further determines whether an invalidity indicator for the literal load table has been received. If so, the instruction processing circuit flushes the literal load table. The invalidity indicator may be generated responsive to modification of a constant table.

Abstract translation: 公开了删除无效文字负载值以及相关电路，方法和计算机可读介质。 在一个方面，指令处理电路提供包含一个或多个条目的文字加载表，该条目包括地址和缓存的字面负载值。 在指令流中检测到文字加载指令时，指令处理电路确定文字加载表是否包含具有文字加载指令地址的条目。 如果是这样，则指令处理电路从指令流中去除文字加载指令，并将存储在该条目中的缓存的文字加载值提供给至少一个从属指令。 指令处理电路还确定是否已经接收到文字负载表的无效指示符。 如果是这样，指令处理电路刷新文字负载表。 可以响应于常数表的修改来生成无效指示符。

公开(公告)号：US20160217016A1

公开(公告)日：2016-07-28

申请号：US14604845

申请日：2015-01-26

Applicant: QUALCOMM Incorporated

Inventor： Arun Raman ,  Behnam Robatmili

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/4806 ,  G06F9/4881 ,  Y02D10/24

Abstract: A computing device (e.g., a mobile computing device, etc.) may be configured to may be configured to better exploit the concurrency and parallelism enabled by modern multiprocessor architectures by identifying a sequence of tasks via a task dependency controller, commencing execution of a first task in the sequence of tasks, and setting a value of a register so that each remaining task in the sequence of tasks executes after its predecessor task finishes execution without transferring control to a runtime system of the computing device. The task dependency controller may be a hardware component that is shared by the processor cores and/or otherwise configured to transfer control between tasks executing on different processor cores independent of the runtime system and/or without performing the relatively slow and memory-based inter-task, inter-thread or inter-process communications required by conventional solutions.

Abstract translation: 计算设备（例如，移动计算设备等）可以被配置为可以被配置为通过经由任务依赖性控制器识别任务序列来更好地利用现代多处理器架构实现的并发性和并行性，开始执行第一 任务序列中的任务，并设置寄存器的值，使得任务序列中的每个剩余任务在其前任任务完成执行之后执行，而不将控制转移到计算设备的运行时系统。 任务依赖性控制器可以是由处理器核共享的硬件组件和/或另外被配置成在独立于运行时系统的不同处理器核上执行的任务之间传送控制和/或不执行相对较慢和基于存储器的间隔 任务，跨线程或传统解决方案所需的进程间通信。

公开(公告)号：US20150205726A1

公开(公告)日：2015-07-23

申请号：US14262852

申请日：2014-04-28

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Madhukar Nagaraja Kedlaya ,  Dario Suarez Gracia

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/4491 ,  G06F12/0802 ,  G06F2212/452

Abstract: Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Abstract translation: 方面包括用于动态语言的内联高速缓存的硬件加速的计算设备，系统和方法。 可以为动态软件操作的实例初始化内联缓存。 动态软件操作的初始化实例的调用可以由内联高速缓存硬件加速器执行。 可以检查内联高速缓存以确定其数据是当前的。 当数据是最新的时，可以使用相关的在线高速缓存数据来执行动态软件操作的初始化实例。 当数据不是当前的时候，可以为动态软件操作的实例初始化新的内联高速缓存，包括动态软件操作的先前初始化的实例的当前数据。 内联高速缓存硬件加速器可以包括内联高速缓冲存储器，协处理器和/或功能，直到连接到处理器流水线的内联高速缓存流水线为止。