公开(公告)号：US20190196785A1

公开(公告)日：2019-06-27

申请号：US15851390

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Albert Danysh ,  Erich Plondke ,  Eric Mahurin

IPC: G06F7/487 ,  G06F7/485

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F7/523 ,  G06F7/5324

Abstract: A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

公开(公告)号：US20190176838A1

公开(公告)日：2019-06-13

申请号：US15838777

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Reza KAKOEE ,  Rahul Gulati ,  Eric Mahurin ,  Suresh Kumar Venkumahanti ,  Dexter Chun

IPC: B60W50/02 ,  G06F11/10 ,  H03M13/05

Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.

公开(公告)号：US20180081803A1

公开(公告)日：2018-03-22

申请号：US15273366

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  David Hoyle

IPC: G06F12/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0676 ,  G06F9/30036 ,  G06F9/3802 ,  G06F9/3887 ,  G06F12/0215 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/656 ,  H03M7/6011 ,  H03M7/6023

Abstract: A method for storing data at contiguous memory addresses includes, at a single-instruction-multiple-data (SIMD) processor, executing a parallel-prefix valid count instruction to determine a first offset of a first data vector and to determine a second offset of a second data vector that includes valid data and invalid data. The second offset is based on the first offset and a number of positions in the first data vector that are associated with valid data. The method also includes storing first valid data from the first data vector at a first memory address of a memory and storing second valid data from the second data vector at a particular memory address of the memory. The first memory address is based on the first offset and the particular memory address is based on the second offset.