公开(公告)号：US11669747B2

公开(公告)日：2023-06-06

申请号：US16667821

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Rexford Alan Hill ,  Eric Wayne Mahurin ,  Aaron Douglass Lamb ,  Albert Danysh ,  Erich Plondke ,  David Hoyle

IPC: G06N5/00 ,  G06N5/01 ,  G06N3/08 ,  H03M7/24 ,  G06F17/17 ,  G06N3/048 ,  H03K19/21 ,  H03K19/20

CPC classification number: G06N5/01 ,  G06F17/17 ,  G06N3/048 ,  G06N3/08 ,  H03M7/24 ,  H03K19/20 ,  H03K19/21

Abstract: A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.

公开(公告)号：US20190354508A1

公开(公告)日：2019-11-21

申请号：US15981203

申请日：2018-05-16

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Erich Plondke ,  David Hoyle

IPC: G06F15/80 ,  G06F9/30

Abstract: A processor includes a vector register configured to load data responsive to a special purpose load instruction. The processor also includes circuitry configured to replicate a selected sub-vector value from the vector register.

公开(公告)号：US20180081803A1

公开(公告)日：2018-03-22

申请号：US15273366

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  David Hoyle

IPC: G06F12/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0676 ,  G06F9/30036 ,  G06F9/3802 ,  G06F9/3887 ,  G06F12/0215 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/656 ,  H03M7/6011 ,  H03M7/6023

Abstract: A method for storing data at contiguous memory addresses includes, at a single-instruction-multiple-data (SIMD) processor, executing a parallel-prefix valid count instruction to determine a first offset of a first data vector and to determine a second offset of a second data vector that includes valid data and invalid data. The second offset is based on the first offset and a number of positions in the first data vector that are associated with valid data. The method also includes storing first valid data from the first data vector at a first memory address of a memory and storing second valid data from the second data vector at a particular memory address of the memory. The first memory address is based on the first offset and the particular memory address is based on the second offset.

公开(公告)号：US11372804B2

公开(公告)日：2022-06-28

申请号：US15981203

申请日：2018-05-16

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Erich Plondke ,  David Hoyle

IPC: G06F15/00 ,  G06F15/76 ,  G06F15/80 ,  G06F9/30

Abstract: A processor includes a vector register configured to load data responsive to a special purpose load instruction. The processor also includes circuitry configured to replicate a selected sub-vector value from the vector register.

公开(公告)号：US12261695B1

公开(公告)日：2025-03-25

申请号：US18470172

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Dharmaraju ,  Anthony Fanous ,  David Hoyle

IPC: G06F11/00 ,  G06F7/58 ,  H04L1/00

Abstract: Aspects described herein relate to selecting a base representation for an advance offset of a shift register sequence, generating the shift register sequence corresponding to the advance offset based at least in part on the base representation, and processing a signal based at least in part on the shift register sequence.

公开(公告)号：US10162752B2

公开(公告)日：2018-12-25

申请号：US15273366

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  David Hoyle

IPC: G06F12/00 ,  G06F12/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/1009 ,  H03M7/30 ,  G06F13/00 ,  G06F13/28

Abstract: A method for storing data at contiguous memory addresses includes, at a single-instruction-multiple-data (SIMD) processor, executing a parallel-prefix valid count instruction to determine a first offset of a first data vector and to determine a second offset of a second data vector that includes valid data and invalid data. The second offset is based on the first offset and a number of positions in the first data vector that are associated with valid data. The method also includes storing first valid data from the first data vector at a first memory address of a memory and storing second valid data from the second data vector at a particular memory address of the memory. The first memory address is based on the first offset and the particular memory address is based on the second offset.

公开(公告)号：US20180081634A1

公开(公告)日：2018-03-22

申请号：US15273481

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  David Hoyle

IPC: G06F7/544 ,  G06F7/57 ,  G06F9/30

CPC classification number: G06F7/544 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/3004 ,  G06F17/17 ,  G06F2207/5354

Abstract: A method includes retrieving, at a processor, a first instruction for performing a first piecewise Horner's method operation for a polynomial and executing the first instruction. Executing the first instruction causes the processor to perform operations including accessing one or more look-up tables based on an interval of a first function input to determine a first coefficient of the polynomial for the first input range. The operations also include determining a first partial polynomial output of the first piecewise Horner's method operation. Determining the first partial polynomial output includes multiplying a first partial polynomial input with the first function input to generate a first partial value and adding the first coefficient to the first partial value to determine the first partial polynomial output.