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公开(公告)号：US09166577B2
公开(公告)日：2015-10-20
申请号：US14167972
申请日：2014-01-29
Applicant: QUALCOMM Incorporated
Inventor： Niranjan Anand Talwalkar , Sanjay Kasturia
CPC classification number: H03K5/133 , H03C3/403 , H03F1/0294 , H03F3/2178 , H03F3/24 , H03K3/017 , H03K7/00
Abstract: A clock modulator can include two configurable delay units and can receive a baseband signal and a clock signal. The two configurable delay units can generate two delayed clock signals, each with different delay amounts. The delay amounts can be based on the baseband signal. The delayed clock signals can be combined to generate a modulated clock signal. A quadrature modulated clock signal can be generated when a first clock modulator receives a first baseband signal and a first clock signal and a second clock modulator receives a second baseband signal and a second clock signal. The first clock signal can be a ninety-degree phase shifted version of the second clock signal. The modulated clock signal from the first clock modulator can be combined with the modulated clock signal from the second clock modulator to generate the quadrature modulated clock signal.
Abstract translation: 时钟调制器可以包括两个可配置的延迟单元，并且可以接收基带信号和时钟信号。 两个可配置的延迟单元可以产生两个延迟时钟信号，每个具有不同的延迟量。 延迟量可以基于基带信号。 延迟的时钟信号可以被组合以产生调制的时钟信号。 当第一时钟调制器接收第一基带信号和第一时钟信号并且第二时钟调制器接收到第二基带信号和第二时钟信号时，可以产生正交调制时钟信号。 第一个时钟信号可以是第二个时钟信号的九十度相移版本。 来自第一时钟调制器的调制时钟信号可以与来自第二时钟调制器的调制时钟信号组合以产生正交调制时钟信号。
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公开(公告)号：US09014300B2
公开(公告)日：2015-04-21
申请号：US14025602
申请日：2013-09-12
Applicant: QUALCOMM Incorporated
Inventor： Niranjan Anand Talwalkar , Sanjay Kasturia
CPC classification number: H04L27/36 , H04L25/028 , H04L25/4902 , H04L27/362
Abstract: A QAM transmitter is disclosed that may reduce the frequency of local clock signals and/or reduce the switching frequency of driver circuits when generating a QAM output signal for transmission. The QAM transmitter may generate a number of PWM signals indicative of in-phase (I) and quadrature (Q) signal components, and then use one or more selected even-order harmonics of the PWM signals to generate the QAM output signal. Odd-order harmonics of the PWM signals may be suppressed by selectively combining the PWM signals, and any remaining unwanted even-order harmonics may be suppressed using filters.
Abstract translation: 公开了一种QAM发射器，其可以在产生用于传输的QAM输出信号时降低本地时钟信号的频率和/或降低驱动器电路的开关频率。 QAM发射机可以产生指示同相（I）和正交（Q）信号分量的多个PWM信号，然后使用PWM信号的一个或多个所选偶次谐波来产生QAM输出信号。 可以通过选择性地组合PWM信号来抑制PWM信号的奇次谐波，并且可以使用滤波器来抑制任何剩余的不需要的偶次谐波。
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公开(公告)号：US20140355697A1
公开(公告)日：2014-12-04
申请号：US14042626
申请日：2013-09-30
Applicant: QUALCOMM Incorporated
Inventor： Gregory Allen Magin , Faisal Mahmood Shad , Lawrence Winston Yonge, III , Sanjay Kasturia , Niranjan Anand Talwalkar
CPC classification number: H04L1/004 , H04B3/54 , H04B3/542 , H04B3/56 , H04B2203/5408 , H04B2203/542 , H04B2203/5425 , H04B2203/5483 , H04B2203/5491
Abstract: A powerline communication (PLC) device can be configured to execute functionality for zero cross sampling and detection. When the PLC device is directly coupled to a high-voltage PLC network, the PLC device can comprise printed safety capacitors in series with a high-voltage input AC powerline signal to safely couple the high-voltage AC powerline signal to the low-voltage processing circuit. The PLC device can also comprise an ADC to sample a scaled AC powerline signal and to obtain zero cross information. When the PLC device is part of an embedded PLC application, dynamic loading can affect the integrity of a low voltage zero cross signal that is used to extract zero cross information. After digitizing the zero cross signal, the PLC device can execute functionality to minimize/eliminate voltage drops caused by dynamic loading and obtain the zero cross information.
Abstract translation: 电力线通信（PLC）设备可以配置为执行零交叉采样和检测的功能。 当PLC设备直接耦合到高压PLC网络时，PLC设备可以包括与高压输入AC电力线信号串联的印刷安全电容器，以将高压AC电力线信号安全地耦合到低压处理 电路。 PLC设备还可以包括ADC以对缩放的AC电力线信号进行采样并获得零交叉信息。 当PLC设备是嵌入式PLC应用的一部分时，动态加载会影响用于提取零交叉信息的低电压零交叉信号的完整性。 数字化零交叉信号后，PLC设备可以执行功能来最小化/消除由动态负载引起的电压降并获得零交叉信息。
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