公开(公告)号：US20240311317A1

公开(公告)日：2024-09-19

申请号：US18674138

申请日：2024-05-24

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US12094515B2

公开(公告)日：2024-09-17

申请号：US17890022

申请日：2022-08-17

Applicant: QUALCOMM INCORPORATED

Inventor： Victor Van Der Veen ,  Pankaj Deshmukh ,  Behnam Dashtipour ,  David Hartley ,  Mosaddiq Saifuddin

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4096

Abstract: An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.

公开(公告)号：US20240062800A1

公开(公告)日：2024-02-22

申请号：US17890022

申请日：2022-08-17

Applicant: QUALCOMM Incorporated

Inventor： Victor Van Der Veen ,  Pankaj Deshmukh ,  Behnam Dashtipour ,  David Hartley ,  Mosaddiq Saifuddin

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4096

Abstract: An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.

公开(公告)号：US11907141B1

公开(公告)日：2024-02-20

申请号：US17929946

申请日：2022-09-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Subbarao Palacharla

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0623

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

公开(公告)号：US11360897B1

公开(公告)日：2022-06-14

申请号：US17231867

申请日：2021-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor

IPC: G06F12/0831 ,  G06F12/0864 ,  G06F13/40 ,  G06F13/16 ,  G06F12/02

Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.