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    Memory system with adaptive refresh
    1.
    发明授权
    Memory system with adaptive refresh 有权

    公开(公告)号：US12038855B2

    公开(公告)日：2024-07-16

    申请号：US17650455

    申请日：2022-02-09

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F13/16

    CPC classification number: G06F13/1668

    Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

    Multiple-core memory controller
    2.
    发明授权
    Multiple-core memory controller 有权

    公开(公告)号：US12153531B2

    公开(公告)日：2024-11-26

    申请号：US18059937

    申请日：2022-11-29

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F13/16

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

    Reducing latency in pseudo channel based memory systems
    3.
    发明授权
    Reducing latency in pseudo channel based memory systems 有权

    公开(公告)号：US11893240B2

    公开(公告)日：2024-02-06

    申请号：US17452606

    申请日：2021-10-28

    Applicant: QUALCOMM Incorporated

    Inventor： Shyamkumar Thoziyoor ,  Pankaj Deshmukh ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

    Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

    EFFICIENCY MODE IN A MEMORY SYSTEM
    4.
    发明申请
    EFFICIENCY MODE IN A MEMORY SYSTEM 有权

    公开(公告)号：US20250068574A1

    公开(公告)日：2025-02-27

    申请号：US18454658

    申请日：2023-08-23

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Subbarao Palacharla ,  Alain Artieri

    IPC: G06F13/16 ,  G06F1/3234 ,  G06F13/28

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support an efficient mode for reducing power consumption in a memory module while maintaining access to all contents of memory. In a first aspect, a method includes communicating, by a memory module, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; communicating second data stored in the second plurality of banks to the host device through a second sub-channel in the first operating mode; receiving a command to enter a second operating mode; and communicating third data stored in the first plurality of banks and fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode. Other aspects and features are also claimed and described.

    Metadata registers for a memory device
    5.
    发明授权
    Metadata registers for a memory device 有权

    公开(公告)号：US12159033B2

    公开(公告)日：2024-12-03

    申请号：US18047493

    申请日：2022-10-18

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Michael Hawjing Lo ,  Subbarao Palacharla ,  Olivier Alavoine

    IPC: G06F3/06

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

    MEMORY SYSTEM WITH ADAPTIVE REFRESH
    6.
    发明公开
    MEMORY SYSTEM WITH ADAPTIVE REFRESH 审中-公开

    公开(公告)号：US20230305971A1

    公开(公告)日：2023-09-28

    申请号：US17650455

    申请日：2022-02-09

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F13/16

    CPC classification number: G06F13/1668

    Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

    Dynamic rowhammer management
    7.
    发明授权
    Dynamic rowhammer management 有权

    公开(公告)号：US12211543B2

    公开(公告)日：2025-01-28

    申请号：US17940430

    申请日：2022-09-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： Victor Van Der Veen ,  Pankaj Deshmukh ,  Behnam Dashtipour ,  David Hartley

    IPC: G11C11/4078 ,  G06F13/16 ,  G11C7/10 ,  G11C11/406

    Abstract: Mitigating or managing an effect known as “rowhammer” upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directed to the DRAM device and count the number of the row activation commands. The memory controller may send a mitigative refresh command to the DRAM device based on the result of comparing the counted number of row activation commands with the received activation count threshold value.

    MEMORY SYSTEM WITH ADAPTIVE REFRESH
    10.
    发明公开
    MEMORY SYSTEM WITH ADAPTIVE REFRESH 审中-公开

    公开(公告)号：US20240311317A1

    公开(公告)日：2024-09-19

    申请号：US18674138

    申请日：2024-05-24

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F13/16

    CPC classification number: G06F13/1668

    Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

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