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    Static random-access memory (SRAM) array
    1.
    发明授权
    Static random-access memory (SRAM) array 有权
    静态随机存取存储器（SRAM）阵列

    公开(公告)号：US09379014B1

    公开(公告)日：2016-06-28

    申请号：US14803063

    申请日：2015-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Mosaddiq Saifuddin

    IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

    CPC classification number: H01L27/1104

    Abstract: A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning multiple columns of cells. The multiple first source lines include a first source line and a second source line. The second metal layer includes multiple second source lines spanning multiple rows of cells. The SRAM array further includes a set of vias coupled to the multiple first source lines and to the multiple second source lines. A first via of the set of vias is coupled to the first source line and multiple vias of the set of vias are coupled to the second source line. Two vias of the multiple vias that are closest to the first via are each substantially the same distance from the first via.

    Abstract translation: 静态随机存取存储器（SRAM）阵列包括第一金属层和第二金属层。 金属层包括跨多个单元格的多个第一源线。 多个第一源极线包括第一源极线和第二源极线。 第二金属层包括跨越多行单元的多个第二源极线。 SRAM阵列还包括耦合到多个第一源极线和多个第二源极线的一组通孔。 通孔组的第一通孔耦合到第一源极线，并且该组通孔的多个通孔耦合到第二源极线。 最靠近第一通孔的多个通孔的两个通孔各自与第一通孔基本相同。

    Bit remapping system
    5.
    发明授权
    Bit remapping system 有权
    位重映射系统

    公开(公告)号：US09378081B2

    公开(公告)日：2016-06-28

    申请号：US14146628

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

    IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/00 ,  G06F13/16

    CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

    Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

    Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

    BIT REMAPPING SYSTEM
    6.
    发明申请
    BIT REMAPPING SYSTEM 有权
    位重新系统

    公开(公告)号：US20150186198A1

    公开(公告)日：2015-07-02

    申请号：US14146628

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

    Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

    Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

    DRAM access in self-refresh state
    7.
    发明授权
    DRAM access in self-refresh state 有权

    公开(公告)号：US09824742B1

    公开(公告)日：2017-11-21

    申请号：US15249132

    申请日：2016-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4085

    Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.

    DRAM ACCESS IN SELF-REFRESH STATE
    9.
    发明申请
    DRAM ACCESS IN SELF-REFRESH STATE 有权

    公开(公告)号：US20170316818A1

    公开(公告)日：2017-11-02

    申请号：US15249132

    申请日：2016-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4085

    Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.

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