公开(公告)号：US09361230B2

公开(公告)日：2016-06-07

申请号：US14859340

申请日：2015-09-20

Applicant: QUALCOMM Technologies Inc.

Inventor： Jean-Jacques Lecler

IPC: G06F12/08 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F13/4282 ,  G06F2212/622

Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

公开(公告)号：US09280468B2

公开(公告)日：2016-03-08

申请号：US13659781

申请日：2012-10-24

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Jean-Jacques Lecler

IPC: G06F13/38 ,  G06F12/08 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F13/4282 ,  G06F2212/622

Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

Abstract translation: 公开了用于在半导体芯片上的启动器和目标代理之间传送一致性信息的系统和方法。 通过仅使用三个通道的套接字接口执行足够的信息通信来支持完全一致性。 事务请求是在一个通道上发出的，其中给出响应。 干预请求是在与交易响应相同的频道上发布的。 干预措施在第三个频道上给出。 与传统方法相比，这种方法大大降低了高速缓存一致性套接字接口的复杂性。 净效应是更快的逻辑，更小的硅面积，改进的架构性能，以及由相干启动器和目标的设计者降低错误概率。

公开(公告)号：US09225665B2

公开(公告)日：2015-12-29

申请号：US13626766

申请日：2012-09-25

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler ,  Boris Boutillier

IPC: H04L12/933 ,  G06F12/12 ,  G06F15/78

CPC classification number: H04L49/109 ,  G06F12/126 ,  G06F15/7825

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract translation: 本发明是事务接口协议，其中接口协议在每个请求和响应信道中具有事务标识符信号。 它在目标网络接口单元（NIU）主机和通过事务接口直接连接的启动器NIU从站之间使用。 目标NIU响应信道使用事务ID信号来识别与相应请求相关联的上下文阵列中的条目。 目标NIU和启动器NIU的耦合使得能够形成包括多个片上网络（NoC）的片上互连，其中互连的拓扑更简单，更小，更快，并且具有更低的延迟。