公开(公告)号：US20140149687A1

公开(公告)日：2014-05-29

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而不进行修改或副作用。

公开(公告)号：US09471538B2

公开(公告)日：2016-10-18

申请号：US13626758

申请日：2012-09-25

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler ,  Boris Boutillier

IPC: G06F15/78 ,  G06F13/364 ,  G06F11/07 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F11/0745 ,  G06F13/364 ,  G06F13/4059

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

公开(公告)号：US09465749B2

公开(公告)日：2016-10-11

申请号：US13969559

申请日：2013-08-17

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/02 ,  G06F12/10 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract translation: 具有预取地址发生器的系统，其耦合到包括翻译高速缓存的系统转换后备缓冲器。 发送预取请求以进行页面地址转换，以便将来预测未来的正常请求。 预取请求被过滤，只能发布用于不太可能在翻译缓存中的地址转换。 待处理的预取请求仅限于可配置或可编程的数字。 这种系统是从硬件描述语言表示模拟的。

公开(公告)号：US09110689B2

公开(公告)日：2015-08-18

申请号：US13680399

申请日：2012-11-19

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Jean-Jacques Lecler

IPC: G06F9/00 ,  G06F17/50 ,  G06F9/445 ,  G06F9/38

CPC classification number: G06F9/445 ,  G06F9/3875 ,  G06F17/505 ,  G06F2217/84

Abstract: The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

Abstract translation: 通过应用求解器确定片上系统的数据路径内的多个可选流水线级的最佳配置。 求解器包括以下变量：将模块物理放置在芯片的平面图中; 信号传播时间; 逻辑门切换时间; 每个模块端口的信号到达时间，时钟沿之后; 每个流水线阶段的到达时间; 以及每个可选流水线阶段的激活状态的布尔值。 最佳配置确保了在可能的情况下满足流水线阶段可能的最低成本的时序约束。

公开(公告)号：US20140095809A1

公开(公告)日：2014-04-03

申请号：US13941483

申请日：2013-07-13

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent MOLL ,  Jean-Jacques Lecler ,  Jonah Proujansky-Bell

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Abstract translation: 具有数据缓冲存储器的一致性控制器，其小于待处理的读取数据请求的数量。 数据缓冲区仅分配给与另一待处理请求的ID匹配的请求。 如果所有的snoops都收到响应，那么缓冲区被解除分配，其中没有一个包含数据。 包含干净数据的缓冲区会丢弃其数据，并将其重新分配给以后的请求。 丢弃的数据随后从目标读取。 当所有缓冲区充满了具有待处理订单ID的脏数据请求时，它们被分流到请求队列中以供稍后服务。 脏数据可能会被阻塞到相关代理上，以使缓冲区可用于重新分配。 因此，一致性控制器可以对超过数据存储器中的缓冲器数量的数据量发出窥探和目标请求。

公开(公告)号：US09563560B2

公开(公告)日：2017-02-07

申请号：US13938675

申请日：2013-07-10

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract translation: 一个一致性控制器（例如在片上系统中使用的控制器）能够向相干缓存发出不同类型的监听。 一致性控制器根据引起窥探或系统状态或两者的请求的类型选择窥探的类型。 通过这样做，一致的高速缓存在它们具有足够的吞吐量时提供数据，并且当它们没有足够的吞吐量时不需要提供数据。

公开(公告)号：US20150019776A1

公开(公告)日：2015-01-15

申请号：US13941537

申请日：2013-07-14

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Jean-Jacques Lecler ,  Jonah Proujansky-Bell ,  Philippe Boucard

IPC: G06F13/362

CPC classification number: G06F13/1605

Abstract: The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed.

Abstract translation: 本发明提供了一种用于半导体知识产权核心之间的交易接口。 待处理事务的紧急属性可以通过接口的特殊类型的事务来更改。 紧急性可以增加，至少提高一个指定的值，或者更改为指定的值。 对于具有多个待处理事务的接口，可以使用掩码来指示一个或多个ID，其事务应该更改。

公开(公告)号：US08930638B2

公开(公告)日：2015-01-06

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM Technologies, Inc.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而无需修改或副作用。

公开(公告)号：US20140143531A1

公开(公告)日：2014-05-22

申请号：US13680399

申请日：2012-11-19

Applicant: QUALCOMM TECHNOLOGIES, INC. ,  ARTERIS SAS

Inventor： Jean-Jacques Lecler

IPC: G06F9/445

CPC classification number: G06F9/445 ,  G06F9/3875 ,  G06F17/505 ,  G06F2217/84

Abstract: The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

Abstract translation: 通过应用求解器确定片上系统的数据路径内的多个可选流水线级的最佳配置。 求解器包括以下变量：将模块物理放置在芯片的平面图中; 信号传播时间; 逻辑门切换时间; 每个模块端口的信号到达时间，时钟沿之后; 每个流水线阶段的到达时间; 以及每个可选流水线阶段的激活状态的布尔值。 最佳配置确保了在可能的情况下满足流水线阶段可能的最低成本的时序约束。

公开(公告)号：US09882839B2

公开(公告)日：2018-01-30

申请号：US14720947

申请日：2015-05-25

Applicant: QUALCOMM Technologies Inc.

Inventor： Philippe Boucard ,  Jean-Jacques Lecler

IPC: G06F3/00 ,  H04L12/28 ,  H04L12/935 ,  H04L12/709 ,  H04L12/801 ,  H04L12/933 ,  G06F13/40 ,  H04L29/06

CPC classification number: H04L49/3072 ,  G06F13/4009 ,  G06F2213/0038 ,  H04L45/245 ,  H04L47/10 ,  H04L49/109 ,  H04L69/22 ,  Y02B70/30 ,  Y02D50/30

Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.