公开(公告)号：US20150060887A1

公开(公告)日：2015-03-05

申请号：US14536625

申请日：2014-11-09

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC: H01L29/808 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract translation: 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

公开(公告)号：US08704291B2

公开(公告)日：2014-04-22

申请号：US13739494

申请日：2013-01-11

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC: H01L29/76

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。