公开(公告)号：US07096343B1

公开(公告)日：2006-08-22

申请号：US09538755

申请日：2000-03-30

申请人： Alan David Berenbaum ,  Nevin Heintze ,  Tor E. Jeremiassen ,  Stefanos Kaxiras

发明人： Alan David Berenbaum ,  Nevin Heintze ,  Tor E. Jeremiassen ,  Stefanos Kaxiras

IPC分类号： G06F9/50

CPC分类号： G06F9/3853 ,  G06F9/3851 ,  G06F9/3885

摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.

摘要翻译： 公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。 本发明结合了传统的非常长的指令字架构和传统的多线程体系结构的技术，以减少单个程序内的执行时间以及跨工作负载。 本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。 指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。 分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令。 那些不能分配给功能单元的指令被保留在一个准备运行的寄存器中。 在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。 然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。

公开(公告)号：US20050102428A1

公开(公告)日：2005-05-12

申请号：US10948483

申请日：2004-09-23

申请人： Nevin Heintze ,  Edward Walters

发明人： Nevin Heintze ,  Edward Walters

IPC分类号： G06F12/02 ,  H04L29/06 ,  G06F15/16 ,  G06F12/00

CPC分类号： G06F12/023 ,  H04L69/12

摘要： To support IP routing table longest-prefix matching, a (ternary content-addressable) memory is managed by assigning its locations to interleaved pages and gaps. Each page has zero or more locations assigned to it, where all entries in a page have the same prefix length. Each gap has zero or more empty locations assigned to it. The pages are organized by descending prefix length. Associated with each page is a free-list identifying empty locations in that page. An “invariant” rule may dictate that first and last page locations cannot be empty. Whenever an entry is deleted from the first or last location in a page, that location is shifted (i.e., reassigned) to the adjacent gap. The direction chosen to search for an empty location for inserting a new entry is based on a global measure of the relative fullness of memory regions above and below the new entry's page.

摘要翻译： 为了支持IP路由表最长前缀匹配，通过将其位置分配给交织的页面和间隙来管理（三进制内容可寻址）存储器。 每个页面分配了零个或多个位置，其中页面中的所有条目具有相同的前缀长度。 每个间隙都有零个或多个空的位置分配给它。 页面按降序前缀长度组织。 与每个页面相关联的是一个空白列表，标识该页面中的空白位置。 “不变式”规则可能会规定第一页和最后一页的位置不能为空。 每当从页面中的第一个或最后一个位置删除条目时，该位置被移位（即重新分配）到相邻间隙。 选择搜索用于插入新条目的空位置的方向是基于新条目页面上方和下方的内存区域的相对丰满度的全局度量。

公开(公告)号：US06658551B1

公开(公告)日：2003-12-02

申请号：US09538757

申请日：2000-03-30

申请人： Alan David Berenbaum ,  Nevin Heintze ,  Tor E. Jeremiassen ,  Stefanos Kaxiras

发明人： Alan David Berenbaum ,  Nevin Heintze ,  Tor E. Jeremiassen ,  Stefanos Kaxiras

IPC分类号： G06F900

CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F9/3853

摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet. The split bit informs the hardware when splitting is prohibited. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time, provided the split bit has not been set. Those instructions that cannot be allocated to a functional units are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.

摘要翻译： 公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。 本发明结合了传统的非常长的指令字（VLIW）架构和常规多线程体系结构的技术，以减少单个程序内的执行时间，以及跨工作负载。 本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。 指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。 然而，有时候，当指令包不能被分割而不违反编译器组装的指令包的语义时， 公开了一种分组分割识别位，其允许硬件有效地确定何时可以分割指令分组。 拆分时禁止拆分硬件。 分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令，前提是分裂位尚未设置。 那些不能分配给功能单元的指令将保留在一个即可运行的寄存器中。 在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。 然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。