公开(公告)号：US20140008716A1

公开(公告)日：2014-01-09

申请号：US13931874

申请日：2013-06-29

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yutaka Okuyama ,  Takashi Hashimoto ,  Daisuke Okada

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/823481 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.

Abstract translation: 当通过存储单元的缩放来减小隔离区域的宽度以减小存储单元和相邻存储单元之间的距离时，注入到存储单元的电荷存储膜中的电子或空穴被扩散到 位于隔离区域上方的电荷存储膜彼此干涉并可能损害存储单元的可靠性。 在半导体器件中，存储单元的电荷存储膜延伸到位于相邻存储单元之间的隔离区域。 隔离区域中的电荷存储膜的有效长度大于隔离区域的宽度。 这里，有效长度表示位于隔离区上方的电荷存储膜的区域的长度，其中不存储电荷。