公开(公告)号：US11049869B2

公开(公告)日：2021-06-29

申请号：US16278951

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Shinichiro Abe ,  Takashi Hashimoto ,  Yuto Omizu

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H01L21/027 ,  H01L29/08 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

公开(公告)号：US10031792B2

公开(公告)日：2018-07-24

申请号：US15650282

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tomoya Saito ,  Masamichi Fujito ,  Koichi Ando ,  Takashi Hashimoto

IPC: G11C7/00 ,  G06F11/07

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

公开(公告)号：US09373630B2

公开(公告)日：2016-06-21

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L21/8234 ,  H01L27/115 ,  H01L27/092

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20140008716A1

公开(公告)日：2014-01-09

申请号：US13931874

申请日：2013-06-29

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yutaka Okuyama ,  Takashi Hashimoto ,  Daisuke Okada

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/823481 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.

Abstract translation: 当通过存储单元的缩放来减小隔离区域的宽度以减小存储单元和相邻存储单元之间的距离时，注入到存储单元的电荷存储膜中的电子或空穴被扩散到 位于隔离区域上方的电荷存储膜彼此干涉并可能损害存储单元的可靠性。 在半导体器件中，存储单元的电荷存储膜延伸到位于相邻存储单元之间的隔离区域。 隔离区域中的电荷存储膜的有效长度大于隔离区域的宽度。 这里，有效长度表示位于隔离区上方的电荷存储膜的区域的长度，其中不存储电荷。

公开(公告)号：US11302828B2

公开(公告)日：2022-04-12

申请号：US17084163

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

公开(公告)号：US20180366556A1

公开(公告)日：2018-12-20

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L21/8239

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US20150287736A1

公开(公告)日：2015-10-08

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜形成。 以及位于第一硅区上方的第二硅区。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US11145744B2

公开(公告)日：2021-10-12

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro Abe ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/12 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US10978385B2

公开(公告)日：2021-04-13

申请号：US16655606

申请日：2019-10-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/66 ,  H01L23/522 ,  H01L27/11517 ,  H01L21/768 ,  H01L23/532 ,  H01L21/762 ,  H01L49/02 ,  H01L27/11573 ,  H01L29/94 ,  H01L27/12 ,  H01L27/08 ,  H01L27/06

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

公开(公告)号：US10651188B2

公开(公告)日：2020-05-12

申请号：US16520758

申请日：2019-07-24

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/11568 ,  G11C11/40 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.