公开(公告)号：US06675251B1

公开(公告)日：2004-01-06

申请号：US09551841

申请日：2000-04-18

申请人： Robert Streitenberger ,  Hiroyuki Kawai ,  Yoshitsugu Inoue ,  Junko Kobara

发明人： Robert Streitenberger ,  Hiroyuki Kawai ,  Yoshitsugu Inoue ,  Junko Kobara

IPC分类号： G06F1336

CPC分类号： G06F13/4059

摘要： A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the second ports includes a PCI master, a PCI target and an AGP Target. The bridge further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the second ports and arbitrators for arbitrating a contention between the transactions on the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.

摘要翻译： 桥包括连接到主总线的第一端口和分别连接到第二总线的第二端口。 第一个端口包括一个PCI主站，一个PCI从站和一个AGP主站。 每个第二端口包括PCI主机，PCI目标和AGP目标。 桥还包括在第一端口和第二端口之间形成异步数据路径的多个先进先出存储器和仲裁器，用于仲裁由先进先出形成的数据路径上的事务之间的争用 基于与交易相关的协议的记忆。

公开(公告)号：US06581087B1

公开(公告)日：2003-06-17

申请号：US09620472

申请日：2000-07-20

申请人： Yoshitsugu Inoue ,  Hiroyuki Kawai ,  Junko Kobara ,  Robert Streitenberger

发明人： Yoshitsugu Inoue ,  Hiroyuki Kawai ,  Junko Kobara ,  Robert Streitenberger

IPC分类号： G06F750

CPC分类号： G06F7/485

摘要： In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their fraction parts compared, and a result of each comparison and a sign of each data are used to code a relationship in magnitude between data corresponding to a clipping coordinate and the other data fed. A clip code generated depending on the previously obtained comparison results from exponent part and fraction part compare units, rather than depending on a zero flag according to a result of an addition or a subtraction and a sign of the result of the addition or the subtraction, can rapidly be generated without the circuit increased in scale.

摘要翻译： 在浮点加法器中，将接收到的两个浮点数据加在一起，并从另一个中减去一个这样的数据，在它们的指数部分通过数位匹配单元匹配数字之前，两个数据的比指数部分与其比例部分进行比较， 使用每个比较的结果和每个数据的符号来编码对应于剪切坐标的数据与馈送的其他数据之间的大小关系。 根据先前获得的指数部分和分数部分比较单位的比较结果生成的剪辑代码，而不是根据加法或减法的结果的零标志和加法或减法的结果的符号， 可以快速产生电路，而电路规模不会增加。

公开(公告)号：US06480873B1

公开(公告)日：2002-11-12

申请号：US09478004

申请日：2000-01-05

申请人： Yoshitsugu Inoue ,  Hiroyuki Kawai ,  Junko Kobara ,  Robert Streitenberger ,  Keijiro Yoshimatsu ,  Hiroyasu Negishi

发明人： Yoshitsugu Inoue ,  Hiroyuki Kawai ,  Junko Kobara ,  Robert Streitenberger ,  Keijiro Yoshimatsu ,  Hiroyasu Negishi

IPC分类号： G06F738

CPC分类号： G06F7/556

摘要： A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e., computes 2Z where Z is the selected multiplication bit string, and furnishes the computed base-2 exponential value as the power operation-result XY.

摘要翻译： 电力操作装置包括位操作单元或者根据输入的指数位串Y从对数运算单元对对数基本位串执行位移操作，并将移位的对数基本位串提供为乘法位串。 指数检查单元检查输入指数位串Y是否是基数2的第i个幂，其中i是整数，如果是，则提供选择信号以从位操作单元直接选择乘法位串 。 乘法比特串选择单元当从指数检查单元接收到选择信号时，选择并提供乘法比特串。 相反，乘法比特串选择单元否则从乘数中选择并提供另一乘法比特串。 指数运算单元从乘法位串选择单元对所选择的乘法比特串执行基2指数运算，即计算2Z，其中Z是所选乘法位串，并将计算出的基2指数值作为幂 操作结果XY。

公开(公告)号：US5715436A

公开(公告)日：1998-02-03

申请号：US510125

申请日：1995-08-01

申请人： Hiroyuki Kawai ,  Yoshitsugu Inoue ,  Robert Streitenberger

发明人： Hiroyuki Kawai ,  Yoshitsugu Inoue ,  Robert Streitenberger

IPC分类号： G06T1/20 ,  G06T5/20 ,  G06F15/80 ,  G06T1/60

CPC分类号： G06T1/20

摘要： There is disclosed a high-speed programmable image processing LSI circuit adaptable to image preprocessing, feature extraction, and matching, which includes a DMA transfer control portion (4) for DMA transfer which reads input data from an external memory to transfer the input data to data memories in the LSI circuit; a sequence control portion (8), an instruction memory (7), and an address generating portion (3) which control writing to and reading from the data memories in response to an instruction code; the DMA transfer control portion (4) accommodating a wait time caused during external data transfer to prevent the wait time from affecting instruction code control in the LSI circuit; SIMD type processing units arranged in parallel and connected to output lines of the data memories for completing the process steps of image processing in cooperation with a postprocessing portion which in turn provides an output signal (54) to the exterior and accommodates a wait time at this time.

摘要翻译： 公开了一种适用于图像预处理，特征提取和匹配的高速可编程图像处理LSI电路，其包括用于DMA传输的DMA传输控制部分（4），其从外部存储器读取输入数据以将输入数据传送到 LSI电路中的数据存储器; 序列控制部分（8），指令存储器（7）和地址生成部分（3），其响应于指令代码控制对数据存储器的写入和读取; DMA传送控制部分（4）容纳在外部数据传输期间引起的等待时间，以防止等待时间影响LSI电路中的指令代码控制; SIMD型处理单元并联布置并连接到数据存储器的输出线，用于与后处理部分协作完成图像处理的处理步骤，后处理部分进一步向外部提供输出信号（54）并且在此处提供等待时间 时间。

公开(公告)号：US06272582B1

公开(公告)日：2001-08-07

申请号：US09140317

申请日：1998-08-26

申请人： Robert Streitenberger ,  Hiroyuki Kawai

发明人： Robert Streitenberger ,  Hiroyuki Kawai

IPC分类号： G06F1300

CPC分类号： G06F13/4027

摘要： A PCI-PCI bridge is connected between a primary PCI bus and a secondary PCI bus, and includes a bridge for connecting the secondary PCI bus to the primary PCI bus. The bridge has a type “00” configuration header, and identifies, at the time of configuration, one of a plurality of PCI agents including a VGA device on the secondary PCI bus based on a value of a function number field of the configuration command from the device driver, and that the identified agent to execute configuration.

摘要翻译： PCI-PCI桥接器连接在主PCI总线和辅助PCI总线之间，并且包括用于将辅助PCI总线连接到主PCI总线的桥。 该桥具有类型“00”配置头，并且在配置时，基于辅助PCI总线上的VGA设备，基于配置命令的功能号字段的值来识别配置时的多个PCI代理之一 设备驱动程序，以及所识别的代理执行配置。