公开(公告)号：US07116539B2

公开(公告)日：2006-10-03

申请号：US10611043

申请日：2003-07-01

申请人： Vineet Twari ,  Roberto Alini

发明人： Vineet Twari ,  Roberto Alini

IPC分类号： H02H3/22 ,  H03K3/00

CPC分类号： H03K17/08142 ,  G11B5/012 ,  G11B2005/0013 ,  H03K17/102

摘要： A driver circuit includes a CMOS stage and switch functionalities for performing certain tasks. One task is to selectively block exposure of the CMOS stage to reference voltage(s). Another task is to selectively protect the CMOS stage during transient operation. Yet another task is to block leakage current from flowing from the CMOS stage to ground.

摘要翻译： 驱动器电路包括用于执行某些任务的CMOS级和开关功能。 一个任务是选择性地阻止CMOS级的参考电压的暴露。 另一个任务是在瞬态操作期间选择性地保护CMOS级。 另一个任务是阻止漏电流从CMOS级流到地。

公开(公告)号：US07035028B2

公开(公告)日：2006-04-25

申请号：US10843823

申请日：2004-05-12

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09

CPC分类号： G11B5/09 ,  G11B2005/0016 ,  H02M3/073

摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US06504666B1

公开(公告)日：2003-01-07

申请号：US09651561

申请日：2000-08-30

申请人： Giuseppe Patti ,  Roberto Alini

发明人： Giuseppe Patti ,  Roberto Alini

IPC分类号： G11B502

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

摘要： A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device and a current sink circuits coupled to each terminal of the write head, for selectively sourcing current to and sinking current from the write head, respectively. A clamp device is coupled to each write head terminal to selectively clamp the write head terminals to steady state intermediate voltage levels. The circuit further includes a control circuit for individually activating the pull-up devices, the current sink circuits and the clamp devices. In particular, when reversing the direction of current flow through the write head from a first direction in which current is provided to the write head via the write head terminal to a second direction in which current is drawn from the write head from the write head terminal, the appropriate pull-up device is activated for a predetermined period of time. The clamp device coupled to the temporarily activated pull-up device is thereafter activated to clamp the corresponding write head terminals to the steady state intermediate voltage levels.

摘要翻译： 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 该电路包括耦合到写入头的每个端子的上拉装置和电流吸收电路，用于分别选择性地将电流从写入头提供到和吸收电流。 夹持装置耦合到每个写入头端子，以将写入端子选择性地钳位到稳定的中间电压电平。 电路还包括用于单独激活上拉装置，电流吸收电路和钳位装置的控制电路。 特别地，当将写入头的电流的方向从写入头的第一方向从写入头终端提供到写入头的第一方向反转到来自写入头的写入头的电流的第二方向 ，适当的上拉装置被激活一段预定的时间。 此后激活耦合到临时激活的上拉装置的钳位装置，以将相应的写头终端钳位到稳态中间电压电平。

公开(公告)号：US06252450B1

公开(公告)日：2001-06-26

申请号：US09393058

申请日：1999-09-09

申请人： Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

发明人： Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

IPC分类号： H03K1756

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

摘要： A method and circuit is disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head through the terminal. The circuit further includes parallel-connected first and second current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. The circuit further includes a control circuit for individually activating the pull-up device and the first and second current sink circuits. In particular, when reversing the direction of current flow through the write head from a first direction in which current is provided to the write head via the write head terminal to a second direction in which current is drawn from the write head from the write head terminal, both the first and second current sink circuits are activated by the control circuit. When the current in the write head nears the desired destination current level, the second current sink circuit is deactivated and the pull-up device is thereafter immediately activated for a predetermined period of time. The pull-up device is deactivated as the current in the write head approaches a constant value. Due to the deactivation of the second current sink circuit and the temporary activation of the pull-up device, current overshoot and undershoot of the write head current is minimized.

摘要翻译： 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 电路包括耦合到写入头的终端的上拉装置，用于通过终端选择性地向写入头提供电流。 电路还包括并联的第一和第二电流吸收电路，每个电路都耦合到写入头终端，并被选择性地激活以经由写入头终端从写入头抽取电流。 电路还包括用于单独激活上拉装置和第一和第二电流吸收电路的控制电路。 特别地，当将写入头的电流的方向从写入头的第一方向从写入头终端提供到写入头的第一方向反转到来自写入头的写入头的电流的第二方向时 第一和第二电流吸收电路都由控制电路激活。 当写头中的电流接近期望的目的地电流电平时，第二电流吸收电路被去激活，然后上拉装置立即激活预定时间段。 随着写入头中的电流接近恒定值，上拉器件被禁用。 由于第二电流吸收电路的去激活和上拉装置的暂时激活，写头电流的电流过冲和下冲被最小化。

公开(公告)号：US06067198A

公开(公告)日：2000-05-23

申请号：US448047

申请日：1995-05-23

申请人： Maurizio Zuffada ,  Paolo Gadducci ,  David Moloney ,  Roberto Alini

发明人： Maurizio Zuffada ,  Paolo Gadducci ,  David Moloney ,  Roberto Alini

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B5/035 ,  H03H7/30

CPC分类号： G11B5/09 ,  G11B20/10009

摘要： A device comprises a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter, and two distinct and parallel sampling channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two sampling channels each comprise an analog-to-digital converter and a Viterbi detector arranged in series and operating according to sampling sequences that alternate with one another.

摘要翻译： 一种器件包括可变增益输入放大器，低通模拟滤波器，横向连续时间模拟滤波器以及插在横向模拟滤波器和RLL-NRZ解码器之间的两个截然不同和并行的采样通道。 两个采样通道各自包括串联的模数转换器和维特比检测器，并根据彼此交替的采样序列进行操作。

公开(公告)号：US5394112A

公开(公告)日：1995-02-28

申请号：US35329

申请日：1993-03-22

申请人： Roberto Alini ,  Francesco Rezzi ,  Gianfranco Vai ,  Marco Gregori

发明人： Roberto Alini ,  Francesco Rezzi ,  Gianfranco Vai ,  Marco Gregori

IPC分类号： H03H11/04 ,  H03H11/54 ,  G05F1/00 ,  G05F5/00

CPC分类号： H03H11/0422 ,  H03F1/302 ,  H03F3/45089 ,  H03F3/45484 ,  H03H11/54 ,  H03F2203/45418 ,  H03F2203/45564 ,  H03F2203/45594 ,  H03F2203/45622 ,  H03F2203/45626 ,  H03F2203/45628 ,  H03F2203/45674 ,  H03F2203/45702

摘要： An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.

摘要翻译： 一种集成电路跨导级，其抑制了对差分跨导级的温度和生产工艺变量的依赖。 使用负反馈关系，其中跨导级的输出连接到附加电流发生器（以精密外部电阻器为基准），连接到电容器，以及连接到PMOS晶体管的栅极，PMOS晶体管将电流源源于 偏振级，其反过来将电流输送到跨导级，或者到多个跨导级。

公开(公告)号：US20050254159A1

公开(公告)日：2005-11-17

申请号：US10843823

申请日：2004-05-12

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09 ,  G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  H02M3/07

CPC分类号： G11B5/09 ,  G11B2005/0016 ,  H02M3/073

摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US20050231843A1

公开(公告)日：2005-10-20

申请号：US10824096

申请日：2004-04-14

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09 ,  G05F3/26 ,  G11B5/02 ,  H04L25/02

CPC分类号： G11B5/02

摘要： A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

摘要翻译： 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

公开(公告)号：US06456148B2

公开(公告)日：2002-09-24

申请号：US09839511

申请日：2001-04-20

申请人： Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

发明人： Giuseppe Patti ,  Roberto Alini ,  Gilles P. DeNoyer

IPC分类号： H03K1756

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

摘要： A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head though the write head terminal. The circuit further includes parallel-connected current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. A first transistor is connected in series between the pull-up device and the write head terminal and biased to provide a voltage differential between the write head terminal and the pull-up device. A second transistor is connected in series between the write head terminal and the current sink circuits and biased to provide a voltage differential between the write head terminal and the current sink circuits.

摘要翻译： 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 该电路包括耦合到写入头的终端的上拉装置，用于通过写入头终端选择性地向写入头提供电流。 电路还包括并联连接的电流吸收电路，每个电路都耦合到写入头终端，并被选择性地激活以经由写头终端从写入头抽取电流。 第一晶体管串联连接在上拉器件和写入端子之间，并被偏置以在写入头端子和上拉器件之间提供电压差。 第二晶体管串联连接在写入头端子和电流吸收电路之间，并被偏置以在写入头端子和电流吸收电路之间提供电压差。

公开(公告)号：US06362681B1

公开(公告)日：2002-03-26

申请号：US09461782

申请日：1999-12-15

申请人： Giacomino Bollati ,  Roberto Alini ,  Daniele Ottini ,  Melchiorre Bruccoleri

发明人： Giacomino Bollati ,  Roberto Alini ,  Daniele Ottini ,  Melchiorre Bruccoleri

IPC分类号： H03K500

CPC分类号： H03H11/0422

摘要： A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

摘要翻译： 具有可编程均衡的低通滤波器包括至少一个二次电池和将输入电压转换为与输入电压的导数成比例的电流的转换器，其被注入到二次电池的节点上以引入两个实际和相对的零 在滤波器的传递函数中。 低通滤波器包括在功能上串联连接的两个结构相似的电路。 每个电路包括一个二次电池单元和一个具有两个输出端的输入级，输出端通过第一电流输出将电流通过两个电路中的第一个电路中的直接耦合并以相反的方式在相应的二次电池单元的输入电容器中注入 这两个电路中的第二个。 第二电压输出耦合到相应的双二次电池的输入端。