-
公开(公告)号：US07595745B1
公开(公告)日：2009-09-29
申请号：US11836619
申请日：2007-08-09
IPC分类号： H03M1/00
CPC分类号： H03K3/356113
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点将基于控制的第一状态时，开关选择性地将输出节点耦合到第一参考电压 信号。 具有电流源的源极跟随器电路建立第二参考电压。 耦合到开关和源极跟随器电路并且具有逻辑门的逻辑电路在输出节点要从第一状态转变到第二状态时，根据控制信号将输出节点选择性地放电到第二参考电压 州。
-
公开(公告)号：US07511649B1
公开(公告)日：2009-03-31
申请号：US11846292
申请日：2007-08-28
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
IPC分类号： H03M1/66
CPC分类号： H03K17/6871 , H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压 第一个状态 第二MOS晶体管具有耦合到输出节点的源极和耦合到偏置电压的栅极。 当输出节点处于第二状态时，电流源电路选择性地偏压第二MOS晶体管，以充当源跟随器电路的一部分。 另外，存储器电路具有耦合到输出节点的输入和输出。 存储器电路被配置为当输出节点从第一状态转换到第二状态时临时存储输出节点的布尔值。 此外，放电电路耦合到输出节点和第二参考电压。 放电电路被配置为当输出节点从第一状态转变到第二状态时临时提供输出节点与第二参考电压之间的放电路径。 放电电路具有耦合到存储器电路的输出的第一输入和耦合到控制信号的第二输入。 控制信号表示输出节点要从第一状态转换到第二状态。
-
公开(公告)号：US6043943A
公开(公告)日：2000-03-28
申请号：US846782
申请日：1997-04-30
申请人： Francesco Rezzi , Giuseppe Patti
发明人： Francesco Rezzi , Giuseppe Patti
CPC分类号： G11B5/012 , G11B20/10009 , G11B5/09 , G11B2005/0016
摘要： A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.
摘要翻译： 一种用于校正由磁阻头产生的响应信号中的不对称的方法和电路。 磁阻头产生响应信号以传送从磁性介质存储装置读取的数字信息。 通过平方输出信号，调制平方输出信号，以及从响应信号中减去经调制的平方输出信号以产生输出信号，以负反馈方式校正不对称性。 该电路采用差分放大器作为输入级和吉尔伯特乘法器电路对输出信号进行平方。
-
4.发明授权System and method for error correction of digitized phase signals from MR/GMR head readback waveforms 失效用于MR / GMR头回读波形数字化相位信号纠错的系统和方法公开(公告)号：US06654924B1
公开(公告)日：2003-11-25
申请号：US09675857
申请日：2000-09-29
IPC分类号： H03M1300
CPC分类号： H03M13/095 , G11B20/1813 , H03M5/145 , H03M13/39
摘要： A system and method for algebraically correcting errors in complex digitized phase signals from a magneto-resistive or giant magneto-resistive (MR/GMR) head readback waveform includes a data state machine that encodes phase symbols into data bits in accordance with, e.g., the (1, 10) constraint and a parity state machine that generates parity symbols such that a single inserted parity symbol does not violate the (1, 7) constraint in a run length limited code and furthermore the data following the insertion will not violate the (1, 10) constraint in a run length limited code. The state machines can be used as a trellis to perform maximum likelihood decoding on received coded data, thus performing soft algebraic error detection on received data. The invention thus guarantees better overall error rate performance than hard decision post processing of blocks of detected bits by a parity check matrix which is otherwise vulnerable to loss of bit synchronization at high linear density recording.
摘要翻译： 用于代数校正来自磁阻或巨磁阻（MR / GMR）磁头回读波形的复数数字相位信号中的误差的系统和方法包括：数据状态机，其将相位符号编码为数据位，例如， （1,10）约束和产生奇偶校验符号的奇偶校验状态机，使得单个插入的奇偶校验符号不违反游程长度限制代码中的（1,7）约束，此外，插入之后的数据将不会违反（ 1，10）在运行长度限制代码中的约束。 状态机可以用作网格，对接收到的编码数据进行最大似然解码，从而对接收到的数据执行软代数误差检测。 因此，本发明保证比通过奇偶校验矩阵的硬判决后处理检测到的比特的更好的总体错误率性能，否则在高线性密度记录时易于丢失比特同步。
-
5.发明授权公开(公告)号：US06604204B1
公开(公告)日：2003-08-05
申请号：US09410274
申请日：1999-09-30
申请人： Hakan Ozdemir , Francesco Rezzi
发明人： Hakan Ozdemir , Francesco Rezzi
IPC分类号： H04L700
CPC分类号： H03M13/6343 , G11B20/16 , H03M13/41 , H03M13/4107 , H03M13/6502 , H04L7/041 , H04L7/042 , H04L7/046
摘要： A synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark. For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector. Furthermore, the synchronizer circuit can recover the sync mark by executing state-transition routines in alignment with the input signal. For example, one can align the synchronizer circuit's state-transition routines to the preamble of the read signal. Such alignment increases the circuit's noise immunity, and thus allows the circuit to recover the sync mark from a read signal having a SNR that is lower than the minimum read-signal SNR of prior sync-recovery circuits. Furthermore, such alignment reduces the time needed for the circuit to reliably detect the sync mark, and thus allows one to shorten the pad of the data forerunner.
摘要翻译： 同步器电路包括输入端子，输出端子和耦合到输入和输出端子的恢复电路。 输入端子接收包括同步标记的输入信号，并且恢复电路可操作以从输入信号中恢复同步标记，并响应于恢复的同步标记在输出端产生同步信号。 例如，这样的同步器电路可以从读取信号恢复同步标记，并定位与电路分离的维特比检测器的数据流的开始。 通过在单独的电路中执行同步恢复功能，可以降低维特比检测器的复杂度并提高数据恢复速度。 此外，同步器电路可以通过执行与输入信号对准的状态转换例程来恢复同步标记。 例如，可以将同步器电路的状态转换例程对准读取信号的前导码。 这种对准增加了电路的抗噪声能力，从而允许电路从具有低于先前同步恢复电路的最小读信号SNR的SNR的读信号中恢复同步标记。 此外，这种对准减少了电路可靠地检测同步标记所需的时间，并且因此允许缩短数据前端的焊盘。
-
6.发明授权Method and apparatus for reading and writing gray code servo data to magnetic medium using synchronous detection 失效使用同步检测将灰度伺服数据读写写入磁介质的方法和装置公开(公告)号：US06201652B1
公开(公告)日：2001-03-13
申请号：US09087364
申请日：1998-05-29
申请人： Francesco Rezzi , Hakan Ozdemir
发明人： Francesco Rezzi , Hakan Ozdemir
IPC分类号： G11B509
CPC分类号： G11B20/18 , G11B5/59616 , G11B5/59688 , G11B27/3027 , G11B2220/20
摘要： A method for synchronously detecting servo information from a data disk includes reading servo information from a disk and passing the servo information signal through a Viterbi detector. The disk is encoded in a known data format from Gray code data to obtain a servo information signal, the encoded Gray code data being constrained to allow no more and no fewer than two “1” states to sequentially occur. The Viterbi detector is modified to eliminate state changes that do not occur within the constrained encoded Gray code data.
摘要翻译： 从数据盘同时检测伺服信息的方法包括从盘读取伺服信息并通过维特比检测器传递伺服信息信号。 磁盘以格雷码数据的已知数据格式进行编码以获得伺服信息信号，编码的格雷码数据被约束以允许不再有不少于两个“1”状态顺序发生。 维特比检测器被修改以消除在约束编码的格雷码数据内不发生的状态变化。
-
7.发明授权Method for erasing a common mode current signal and transconductor assembly using such method 失效使用这种方法擦除共模电流信号和跨导体组件的方法
公开(公告)号：US5696457A
公开(公告)日：1997-12-09
申请号：US454649
申请日：1995-05-31
CPC分类号： H03F3/45964 , H03F3/45278 , H03F3/45717 , H03F2203/45024 , H03F2203/45068 , H03F2203/45078 , H03F2203/45394 , H03F2203/45648
摘要： A low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors.
摘要翻译： 一种低压跨导电路，其中第一跨导级的共模增益由不具有差分晶体跨导的第二跨导级（与第一跨导级并联连接）补偿，并且其连接使得其共模 跨导抵消了该级的共模跨导。 这大大降低了输出端的共模电流信号，同时避免了在输入晶体管的源极处的电流吸收器的必要性。
-
公开(公告)号：US5430337A
公开(公告)日：1995-07-04
申请号：US105736
申请日：1993-08-12
CPC分类号： H03F1/3211 , H03F3/45076 , H03F3/45282
摘要： A transconductor stage for high-frequency filters of a type which comprises an input circuit portion having signal inputs and an output circuit portion, incorporates a pair of field-effect transistors having respective gate and source terminals in common, and has the output portion formed of a pair of bipolar transistors connected to the aforesaid field-effect transistors.
摘要翻译： 一种用于包括具有信号输入的输入电路部分和输出电路部分的类型的高频滤波器的跨导级，包括一对共同具有各自的栅极和源极端子的场效应晶体管，并且具有由 连接到上述场效应晶体管的一对双极晶体管。
-
公开(公告)号：US07629909B1
公开(公告)日：2009-12-08
申请号：US11836628
申请日：2007-08-09
IPC分类号： H03M1/00
CPC分类号： H03K19/00361 , H03K17/162 , H03M1/742
摘要： In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.
摘要翻译： 在转换控制信号的电压范围的电路中，当输出节点处于第一状态时，第一开关基于控制信号将输出节点选择性地耦合到第一参考电压。 当输出节点处于第二状态时，第二开关基于控制信号选择性地建立第二参考电压，第二状态是第一状态的逻辑补码。 反馈控制回路耦合到输出节点以响应于输出节点处的电压波动来维持第二参考电压。 反馈控制回路包括电流镜和耦合到电流镜的晶体管。 晶体管通过来自输出节点的反馈来控制，以修改由电流镜所建立的偏置电流，从而抵消电压波动。
-
公开(公告)号：US07609186B1
公开(公告)日：2009-10-27
申请号：US11836584
申请日：2007-08-09
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点处于第一状态时，第一晶体管选择性地将输出节点耦合到第一参考电压。 当输出节点要从第一状态转变到第二状态时，第二晶体管通过电阻器选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。 源跟随器电路具有耦合到输出节点并具有动态电流源的源极跟随器输出，动态电流源具有耦合到电阻器的控制输入。 当输出节点处于第二状态时，第三晶体管选择性地将源极跟随器输出耦合到动态电流源。
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.012 秒)
