公开(公告)号：US20200273858A1

公开(公告)日：2020-08-27

申请号：US16874347

申请日：2020-05-14

Applicant: ROHM CO., LTD.

Inventor： Kentaro NASU ,  Kenji NISHIDA

IPC: H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/06

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

公开(公告)号：US20220084912A1

公开(公告)日：2022-03-17

申请号：US17425212

申请日：2020-02-07

Applicant: ASE JAPAN CO., LTD. ,  ROHM CO., LTD.

Inventor： Susumu FUKUI ,  Takaki TAKAHASHI ,  Kanako DEGUCHI ,  Kentaro NASU

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device includes a first lead, a semiconductor element, a sealing resin, a first plating layer, and a second plating layer. The first lead has a first obverse surface and a first reverse surface facing opposite from each other in a thickness direction and a first recess recessed from the first reverse surface toward the first obverse surface. The semiconductor element is mounted on the first obverse surface. The sealing resin covers the semiconductor element. The first plating layer is formed in contact with the first obverse surface and the first reverse surface. The first recess is exposed from the sealing resin. The first plating layer includes a first portion covering the first reverse surface. The second plating layer is formed in contact with the first recess and the first portion.

公开(公告)号：US20220069119A1

公开(公告)日：2022-03-03

申请号：US17454433

申请日：2021-11-10

Applicant: ROHM CO., LTD.

Inventor： Kentaro NASU

IPC: H01L29/78 ,  H01L29/866 ,  H01L29/423 ,  H01L29/16 ,  H01L29/417 ,  H01L27/02

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

公开(公告)号：US20210398884A1

公开(公告)日：2021-12-23

申请号：US17290087

申请日：2019-11-14

Applicant: ROHM CO., LTD.

Inventor： Kentaro NASU

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L23/00

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

公开(公告)号：US20180096991A1

公开(公告)日：2018-04-05

申请号：US15713015

申请日：2017-09-22

Applicant: ROHM CO., LTD.

Inventor： Kentaro NASU ,  Kenji NISHIDA

IPC: H01L27/088 ,  H01L23/522 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

公开(公告)号：US20170338336A1

公开(公告)日：2017-11-23

申请号：US15597469

申请日：2017-05-17

Applicant: ROHM CO., LTD.

Inventor： Kentaro NASU

IPC: H01L29/78 ,  H01L27/02

CPC classification number: H01L29/7808 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.