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11.
公开(公告)号:US12216560B2
公开(公告)日:2025-02-04
申请号:US18215599
申请日:2023-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyungkeun Lee , Bumjun Kim , Seunghan Lee
Abstract: Disclosed is a method of operating an electronic device which includes a host device and a storage device. The host device includes a processor and a baseboard management controller (BMC), the storage device includes a storage controller and a micro controller unit (MCU), and the BMC and the MCU support out-of-band communication. The method of operating the electronic device includes providing, by the BMC, a first request including information about environment data to the MCU through the out-of-band communication, and providing, by the MCU, a first response corresponding to the first request to the BMC through the out-of-band communication.
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公开(公告)号:US20240259303A1
公开(公告)日:2024-08-01
申请号:US18352497
申请日:2023-07-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungsoo Kim , Hyunjoon Yoo , Bumjun Kim , Mehee Yun , Sang-Hwa Jin
IPC: H04L45/00 , H04L45/302 , H04L47/2425
CPC classification number: H04L45/38 , G06F13/4226 , H04L45/3065 , H04L47/2433 , G06F2213/0026
Abstract: A routing method that may be performed by a system on chip of a backplane that is connected between a plurality of hosts and a plurality of devices. The routing method may include: monitoring traffic of the plurality of devices; determining mode types of the plurality of devices according to the monitored traffic; and performing routing to allocate lanes between the plurality of devices and the backplane according to the mode types.
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公开(公告)号:US11800686B2
公开(公告)日:2023-10-24
申请号:US17659766
申请日:2022-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sungchul Hur , Jaehong Park , Bumjun Kim , Yusuf Cinar , Hanhong Lee , Youngseok Hong , Doil Kong , Jaeheon Ma
CPC classification number: H05K7/20436 , G11B33/1426 , H05K1/0201 , H05K1/0203 , H05K7/20163 , G11B33/142
Abstract: A solid state drive (SSD) apparatus includes a case including an air tunnel disposed between an inner plate and an upper wall and an accommodation space between the inner plate and a lower wall. The air tunnel extends in a first direction, and both end parts of the air tunnel are exposed to the outside. A substrate is disposed in the accommodation space. At least one semiconductor chip is disposed on the substrate.
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