公开(公告)号：US11670378B2

公开(公告)日：2023-06-06

申请号：US17499533

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US20200321059A1

公开(公告)日：2020-10-08

申请号：US16825302

申请日：2020-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha Park ,  Chaehoon Kim ,  Sangwan Nam

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.

公开(公告)号：US10339989B2

公开(公告)日：2019-07-02

申请号：US15637099

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon Kim ,  Jin-Young Chun ,  Yunyeong Jeon

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

Abstract: A page buffer includes a pre-charge unit for pre-charging a bit line of a selected memory cell of a memory cell array via a first pre-charge line and pre-charging a sensing node via a second pre-charge line, during a pre-charge time, a bit line connection unit connected between the bit line and the sensing node and including a connecting node connected to the first pre-charge line, the bit line connection unit controlling a voltage of the sensing node, during a develop time, based on a bit line connection control signal and a sensing node voltage control signal, and a data input and output unit for generating sensing data by sensing a level of the voltage of the sensing node, during a sensing time.