公开(公告)号：US11450086B2

公开(公告)日：2022-09-20

申请号：US16617967

申请日：2018-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-su Cho ,  Kyung-hoon Kim ,  Young-hwan Park ,  Suk-jin Kim ,  Hyun-jung Kim ,  Dong-wook Kwon

IPC: G06V10/44 ,  G06F9/26 ,  G06N3/063 ,  G06N3/08

Abstract: Disclosed is an electronic device and method for controlling same. The electronic device comprises: a memory; and a processor which checks an operation instruction for filtering input data of a neural network for each filter of a main pattern selected from a plurality of filters generated according to learning by the neural network, and stores the checked operation instruction in the memory.

公开(公告)号：US11093439B2

公开(公告)日：2021-08-17

申请号：US16143922

申请日：2018-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava prasad Nagaraja ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06F9/30 ,  G06N3/08 ,  G06F15/80 ,  G06F7/544 ,  G06N20/00 ,  G06N3/04 ,  G06N3/063

Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.

公开(公告)号：US11042502B2

公开(公告)日：2021-06-22

申请号：US14757586

申请日：2015-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KWANGWOON UNIVERSITY INDUSTRY-ACADEMIC COLLABORATION FOUNDATION

Inventor： Young-hwan Park ,  Hyunseok Lee ,  Yonggeun Hong ,  Suk-jin Kim

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: An operation processing apparatus is provided. The operation processing apparatus includes a vector operator and cores. The vector operator processes a vector operation with respect to an instruction that uses the vector operation, and each core includes a scalar operator that processes a scalar operation with respect to an instruction that does not use the vector operation. The vector operator is shared by the cores.

公开(公告)号：US10565017B2

公开(公告)日：2020-02-18

申请号：US15669408

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwan Suh ,  Suk-jin Kim ,  Jin-sae Jung ,  Kang-jin Yoon

IPC: G06F9/30 ,  G06N5/04 ,  G06F9/50 ,  G06F9/38

Abstract: A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.

公开(公告)号：US11907826B2

公开(公告)日：2024-02-20

申请号：US15934341

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hoon Kim ,  Young-hwan Park ,  Ki-seok Kwon ,  Suk-jin Kim ,  Chae-seok Im ,  Han-su Cho ,  Sang-bok Han ,  Seung-won Lee ,  Kang-jin Yoon

IPC: G06N3/045 ,  G10L15/16 ,  G06N3/063 ,  G06N20/00 ,  G06N3/044

CPC classification number: G06N3/045 ,  G06N3/044 ,  G06N3/063 ,  G06N20/00 ,  G10L15/16

Abstract: An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.

公开(公告)号：US11675997B2

公开(公告)日：2023-06-13

申请号：US16163772

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/04 ,  G06F17/15 ,  G06F21/52 ,  G06F12/06 ,  G06N5/04 ,  G06N3/063 ,  G06N5/046 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06F12/06 ,  G06F17/15 ,  G06F21/52 ,  G06N3/045 ,  G06N3/063 ,  G06N5/046

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

公开(公告)号：US10782974B2

公开(公告)日：2020-09-22

申请号：US15360271

申请日：2016-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-chul Cho ,  Suk-jin Kim ,  Chul-soo Park ,  Dong-kwan Suh

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/78

Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

公开(公告)号：US10430339B2

公开(公告)日：2019-10-01

申请号：US15107255

申请日：2014-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Kwon ,  Chul-soo Park ,  Suk-jin Kim

IPC: G06F12/0846 ,  G06F12/0815 ,  G06F12/0886 ,  G06F12/02

Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

公开(公告)号：US10409596B2

公开(公告)日：2019-09-10

申请号：US15536351

申请日：2015-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-uk Cho ,  Suk-jin Kim ,  Dong-kwan Suh

IPC: G06F9/30 ,  G06F16/901 ,  G06F12/02 ,  G06F12/06

Abstract: Disclosed is an apparatus comprising: a plurality of memory banks; and a controller for generating a plurality of lookup tables storing data, needed for vector arithmetic operations, copied from data stored in the plurality of memory banks, and generating vector data by reading the data in the generated lookup tables.

公开(公告)号：US10396797B2

公开(公告)日：2019-08-27

申请号：US15520294

申请日：2015-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwan Suh ,  Ki-seok Kwon ,  Young-hwan Park ,  Seung-won Lee ,  Suk-jin Kim

IPC: G06F9/38 ,  G06F15/76 ,  G06F15/173 ,  H03K19/177

Abstract: Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.