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    Direct memory access controller and system for accessing channel buffer
    2.
    发明授权
    Direct memory access controller and system for accessing channel buffer 有权

    公开(公告)号：US10185676B2

    公开(公告)日：2019-01-22

    申请号：US14619783

    申请日：2015-02-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-seok Kwon ,  Suk-jin Kim ,  Do-hyung Kim

    IPC: G06F13/28

    Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

    PROCESSOR AND METHOD OF CONTROLLING THE SAME
    3.
    发明申请
    PROCESSOR AND METHOD OF CONTROLLING THE SAME 审中-公开
    处理器及其控制方法

    公开(公告)号：US20150193375A1

    公开(公告)日：2015-07-09

    申请号：US14568400

    申请日：2014-12-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-seok KWON ,  Suk-jin Kim ,  Do-hyung Kim

    IPC: G06F15/76 ,  G06F9/30

    CPC classification number: G06F15/76 ,  G06F9/30145 ,  G06F9/3877 ,  G06F15/167 ,  G06F15/7867

    Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.

    Abstract translation: 控制处理器的方法包括：从命令缓冲器接收与由第二处理核心处理的第一指令相对应的第一命令，并由第一处理核心开始处理第一命令，在命令缓冲器中存储对应于 在第一命令的处理完成之前由第二处理核心处理的第二指令，以及在完成第一命令的处理之前由第二处理核心开始第三指令的处理。

    Electronic device and control method thereof
    6.
    发明授权
    Electronic device and control method thereof 有权

    公开(公告)号：US11568323B2

    公开(公告)日：2023-01-31

    申请号：US16650083

    申请日：2018-05-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad Nagaraja ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

    IPC: G06N3/04 ,  G06N20/10 ,  G06N3/08

    Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

    Processor and controlling method thereof to process an interrupt
    8.
    发明授权
    Processor and controlling method thereof to process an interrupt 有权

    公开(公告)号：US10318452B2

    公开(公告)日：2019-06-11

    申请号：US15136183

    申请日：2016-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chae-seok Im ,  Dong-kwan Suh ,  Suk-jin Kim ,  Seung-won Lee

    IPC: G06F13/24 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/46

    Abstract: A processor and a control method thereof are processed. The processor includes an instruction fetch module configured to receive a first instruction of an interrupt service routine without backup of data stored in a register in response to processing of the interrupt service routine being requested, a detecting module configured to analyze the received first instruction to determine whether the data stored in the register needs to be changed, an instruction generating module configured to generate a second instruction for storing data in a temporary memory when the stored data is initially changed, an instruction selecting module configured to sequentially select the generated second instruction and first instruction; and a control module configured to perform the second instruction and the first instruction.

    Method of compressing and restoring configuration data
    10.
    发明授权
    Method of compressing and restoring configuration data 有权
    压缩和恢复配置数据的方法

    公开(公告)号：US09344115B2

    公开(公告)日：2016-05-17

    申请号：US14671377

    申请日：2015-03-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-chul Cho ,  Do-hyung Kim ,  Suk-jin Kim ,  Si-hwa Lee

    IPC: H03M7/00 ,  H03M7/30

    CPC classification number: H03M7/60 ,  H03M7/30

    Abstract: A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data.

    Abstract translation: 一种压缩在可重构处理器中使用的配置数据的方法，包括通过组合在两个或多个周期中使用的配置数据来生成一个组合数据，并且生成指示在组合中包括的操作中的两个或更多个周期中的每一个的有效操作的位表 数据。

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