公开(公告)号：US11263018B2

公开(公告)日：2022-03-01

申请号：US16462086

申请日：2017-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Kwon ,  Jae-un Park ,  Dong-kwan Suh ,  Kang-jin Yoon

IPC: G06F9/38 ,  G06F9/30

Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.

公开(公告)号：US10915323B2

公开(公告)日：2021-02-09

申请号：US15520168

申请日：2015-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Kwon ,  Min-wook Ahn ,  Suk-jin Kim ,  Young-hwan Park

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34

Abstract: Provided is a data processing method including the operations of storing, in a register, a first immediate portion included in a first instruction, from among the first immediate portion and a second immediate portion that constitute an immediate value, which is an operand; determining the immediate value by catenating the second immediate portion included in a second instruction with the stored first immediate portion; and performing an operation by using a value indicated by the second instruction and the determined immediate value.

公开(公告)号：US10185676B2

公开(公告)日：2019-01-22

申请号：US14619783

申请日：2015-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Kwon ,  Suk-jin Kim ,  Do-hyung Kim

IPC: G06F13/28

Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

公开(公告)号：US11907826B2

公开(公告)日：2024-02-20

申请号：US15934341

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hoon Kim ,  Young-hwan Park ,  Ki-seok Kwon ,  Suk-jin Kim ,  Chae-seok Im ,  Han-su Cho ,  Sang-bok Han ,  Seung-won Lee ,  Kang-jin Yoon

IPC: G06N3/045 ,  G10L15/16 ,  G06N3/063 ,  G06N20/00 ,  G06N3/044

CPC classification number: G06N3/045 ,  G06N3/044 ,  G06N3/063 ,  G06N20/00 ,  G10L15/16

Abstract: An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.

公开(公告)号：US10481867B2

公开(公告)日：2019-11-19

申请号：US15727093

申请日：2017-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-un Park ,  Jong-hun Lee ,  Ki-seok Kwon ,  Dong-kwan Suh ,  Kang-jin Yoon ,  Jung-uk Cho

IPC: G06F13/16 ,  G06F5/06 ,  G06F9/38 ,  G06F9/52

Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.

公开(公告)号：US10430339B2

公开(公告)日：2019-10-01

申请号：US15107255

申请日：2014-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Kwon ,  Chul-soo Park ,  Suk-jin Kim

IPC: G06F12/0846 ,  G06F12/0815 ,  G06F12/0886 ,  G06F12/02

Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

公开(公告)号：US10396797B2

公开(公告)日：2019-08-27

申请号：US15520294

申请日：2015-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwan Suh ,  Ki-seok Kwon ,  Young-hwan Park ,  Seung-won Lee ,  Suk-jin Kim

IPC: G06F9/38 ,  G06F15/76 ,  G06F15/173 ,  H03K19/177

Abstract: Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.

公开(公告)号：US10366049B2

公开(公告)日：2019-07-30

申请号：US14568400

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Kwon ,  Suk-jin Kim ,  Do-hyung Kim

IPC: G06F9/30 ,  G06F15/76 ,  G06F15/78 ,  G06F9/38 ,  G06F15/167

Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.